Main Area of Research: Digital Systems, Computer Arithmetic and VLSI Design

Research Highlights

Machine Learning and Approximate Computing

Internet-of-Things and Edge Computing

Power Efficient Digital Signal Processors

Past and not so Current Work

Arithmetic Units and Numerical Processors

Power and Thermal Management of Systems-on-Chips

Machine Learning and Approximate Computing

Approximate computing is a promising approach to energy-efficient design of digital systems in many domains such as Machine Learning (ML). The use of specialized data formats in Deep Neural Networks (DNNs), the dominant Machine Learning algorithm, could allow substantial improvements in processing time and power efficiency.

The focus is on applying variable precision formats to ML algorithms. These formats allow to set different precisions for different operations and to tune the precision of given layers of the neural network to obtain higher power efficiency.

Work in the area:

Tunable Floating-Point

Imprecise Arithmetic

Internet-of-Things and Edge Computing

Increasingly sophisticated and computationally intensive algorithms are required for applications running on mobile devices and embedded processors constituting the Internet-of-Things (IoT). These applications include audio and image recognition, machine learning, and security. Today, heavy computations are transferred to servers (the cloud), but in the paradigm of ``Edge" computing, it is desirable to perform the computation locally to decrease latency, network traffic and reduce the overall energy footprint.

In this context, Application Specific Processors (ASPs) are used to accelerate software applications in portable systems and at the Edge. FPGA-based accelerators can be designed and fine tuned to match exactly the algorithm, and FPGAs can be reconfigured at run-time by making the system adaptable to the specific workload.

Moreover, provided a library of ASPs, specific ASPs are loaded on-the-fly in the FPGA, Dynamically-Loaded Hardware Libraries (HLL), and the execution is transfered from the CPU to the FPGA-based accelerator.

Work in the area:

FPGA-based Accelerators

Power Efficient Digital Signal Processors

The main objective is to implement traditional DSP processors (filters, etc.) by using low-power methods to obtain significant reductions in power consumption.

Two main approaches are followed.

Residual Arithmetic

The Residue Number System (RNS) allows the decomposition of a given dynamic range (bit-width) in slices of smaller range on which the computation can be implemented in parallel at higher speed.

Imprecise Arithmetic

Precision in arithmetic operations is traded off with reduced power dissipation. In signal processing, it is possible to have an acceptable quality even introducing some errors.

Work in the area:

Imprecise Arithmetic

Residue Number System based, Fast Architectures for DSP

High-level Power Characterization of Systems implemented on FPGAs

Arithmetic Units and Numerical Processors

This area of research is related to hardware algorithms for numerical computations and their effective implementation in terms of speed of execution, area, and energy.

Emphasys is given to more complicated operations such as division and square-root, and to the implementation of operations in decimal arithmetic.

Links to our work in the area:

Binary Floating-Point Units

Decimal Arithmetic

Ph. D. Dissertation

M.S.'s Thesis

Low Power Design for Arithmetic Structures

Division and Square Root

Power and Thermal Management of Systems-on-Chips

The main objective of this line of work is the study of techniques to reduce the power dissipation, without penalizing the performance, to prevent the temperature to rise in excess, and to increase the reliability.

When it is not possible to reduce the power dissipation any further, the chip temperature rise can be mitigated by changing the power density of the system: by reorganizing the floorplan (statically), or by thermal-aware scheduling the SoC operations (dynamically).

Work in the area:

Thermal Management at Floorplanning Level

Thermal and Reliability Issues in Floating-Point Units

Power Consumption Characterization

Modified by Alberto Nannarelli on Monday October 15, 2018 at 12:08