FPGA-based Accelerators

Dynamically-Loaded Hardware Libraries (HLL)

In this line of work, we developed a hardware framework to dynamically load hardware libraries on reconfigurable platforms (FPGAs). We call this framework Dynamically-Loaded Hardware Libraries (HLL).

Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator.

Results on HLL prototypes (Xilinx's Zynq chipset) show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs.

HLL is also suitable for applications in embedded systems and Internet-of-Things

HLL solution for audio applications

Recent work in the area

  • A. Lomuscio, G. C. Cardarilli, A. Nannarelli, and M. Re, "A Hardware Framework for on-Chip FPGA Acceleration", to appear in Proc. of International Symposium on Integrated Circuits (ISIC 2016)}, Dec. 2016.

  • A. Esposito, A. Lomuscio, G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, A. Nannarelli, and M. Re, "Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications" to appear in Proc of 50th Asilomar Conference on Signals, Systems, and Computers Nov. 2016.

  • G.C. Cardarilli, L. Di Carlo, A. Nannarelli, F. M. Pandolfi, and M. Re, "A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration", Proc. of IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), pp. 291-296, Abu Dhabi, UAE, Dec. 7-10, 2015.

FPGA-based (PCI) Accelerators for Financial Applications

Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors (ASPs) using uncommon operations or number systems.

We designed FPGA-based accelerators for financial applications in the decimal system to implement a telephone billing application, and in binary32 to implement a Monte Carlo simulation for options' pricing.

By comparing the accelerator performance and energy consumption to a software execution of the application, significant speed-up and energy savings, can be obtained by using the accelerator at expenses of a longer development time.

FPGA accelerator connected to CPU via PCI-bus

Relevant work in the area

Modified by Alberto Nannarelli on Tuesday November 08, 2016 at 10:56