Tunable FloatingPoint
Tunable FloatingPoint (TFP)
is a floatingpoint format with adjustable significand and exponent fields bitwidth
Features
 Significand m=[3, 24] bits (including hidden bit). Fraction f=m1.
 Exponent e=[5,8] bits
 Rounding modes
 RTZ Round toward zero (truncation)
 RTN Round to the nearest (round up)
 RTNE Round to the nearest (tie to even)
IEEE 754 roundTiesToEven mode
 RTO Round to odd
 Customazible bias.
By custom bias can "skew" the dynamic range to increase precision.
TFP includes binary32 (m=24, e=8), binary16 (m=11, e=5),
Google's BrainFP (m=8, e=8).
Motivation
 A flexible unit, handling a flexible format, can increase the power efficiency
 Operations can be approximated by reducing the precision
 Different precision/dyn. range in different parts of the algorithm
 Accuracy of reduced precision can be improved by rounding
Publications

A. Nannarelli.
"Variable Precision 16bit FloatingPoint Vector Unit for Embedded Processors",
Proc. of 27th IEEE Symposium on Computer Arithmetic (ARITH 2020),
p. 96102. Portland, USA. 710 June 2020.

A. Nannarelli,
"Tunable FloatingPoint Adder,"
IEEE Transactions on Computers, vol. 68, no. 10, pp. 15531560, Oct. 2019.

A. Nannarelli.
"Fused MultiplyAdd for Variable Precision FloatingPoint",
Proc. of the 32nd IEEE International SystemonChip Conference (SOCC),
p. 342347. Singapore. Sep. 2019.

M. Franceschi, A. Nannarelli and M. Valle,
"Tunable FloatingPoint for Artificial Neural Networks",
Proc. of 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018),
Bordeaux, France. Dec. 2018.

M. Franceschi, A. Nannarelli and M. Valle,
"Tunable FloatingPoint for Embedded Machine Learning Algorithms Implementation",
Proc. of 15th International Conference on Synthesis, Modeling, Analysis
and Simulation Methods and Applications to Circuit Design (SMACD 2018),
p. 8992.
Prague, Czech Republic. 25 July 2018.

A. Nannarelli.
"Tunable FloatingPoint for Energy Efficient Accelerators",
Proc. of 25th IEEE Symposium on Computer Arithmetic (ARITH25),
p. 3340,
Amherst, USA. 2527 June 2018.

A. Nannarelli.
"A MultiFormat FloatingPoint Multiplier for PowerEfficient Operations",
Proc. of the 30th IEEE International SystemonChip Conference (SOCC),
p. 351356. Munich, Germany. Sep. 2017.
Modified by Alberto Nannarelli on
Wednesday October 04, 2023 at 11:49