Decimal Arithmetic
Computers resort to binary arithmetic to have a reduced number of components in order to save area on silicon and to reduce the space of the system.
However, humans are used to deal with the decimal system and, sometimes, binary arithmetic is not so accurate in performing computation of decimals.
Binary floatingpoint cannot exactly represent decimal fractions. For example
10% = 10/100 = (0.1)_{10} = (0.0001100110011001100110011001 .... )_{2}
For these reasons, financial applications implement decimal arithmetic operations in software and run much slower than the corresponding binary operations.
Nowadays, because of the shrinking of devices, it is realistic to design arithmetic units working in decimal arithmetic and to speed up operations done in the decimal system by several times.
In the 2008 revision of IEEE standard 754, the specification to represent decimal floatingpoint numbers
was added to the binary one.
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Work in the area

Decimal FloatingPoint Unit

Decimal Division (DPD/BCD)^{1}

T. Lang, A. Nannarelli. "A Radix10 DigitRecurrence Division Unit: Algorithm and Architecture",
IEEE Transactions on Computers, vol. 56(6), pp. 727739, June 2007.

T. Lang and A. Nannarelli.
"Combined Radix10 and Radix16 Division Unit",
Proc. of 41st Asilomar Conference on Signals, Systems, and Computers,
p. 967971.
Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA.
November 47, 2007.
 ^{1} DPD is Densely Packed Decimal and BCD is
Binary Coded Decimal.

Decimal Division (BID)^{2}

T. Lang and A. Nannarelli.
"Division Unit for Binary Integer Decimals",
Proc. of 20th IEEE International Conference on Applicationspecific Systems, Architectures and Processors (ASAP '09), p. 17, Boston, USA. 79 July 2009.

S. GonzalezNavarro, A. Nannarelli, C. Tsen, M. J. Schulte.
"A Combined Decimal and Binary Floatingpoint Divider",
Proc. of 43rd Asilomar Conference on Signals, Systems, and Computers,
Pacific Grove (CA), USA. Nov. 2009.
 ^{2} BID is
Binary Integer Decimal.

Decimal Multiplication (DPD/BCD)

T. Lang and A. Nannarelli.
"A Radix10 Combinational Multiplier",
Proc. of 40th Asilomar Conference on Signals, Systems, and Computers,
p. 313317.
Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. October 29 
November 1, 2006.

L. Dadda and A. Nannarelli.
"A Variant of a Radix10 Combinational Multiplier",
Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
p. 33703373. Seattle, USA. May 1821, 2008.
Alberto Nannarelli