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02208 Test of Integrated Circuits |
We reserve the right to change the examination syllabus below until the latest time required by DTU rules and regulations.
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Stanley L. Hurst VLSI Testing: digital and mixed analogue/digital techniques IEE Circuits, Devices and Systems Series, Vol. 9 Series editors D.G. Haigh, R.S. Soin and J. Wood The Institution of Electrical Engineers, 1998 ISBN 0-85296-901-5 |
Chapter 1: Introduction | 1 - 16 | |
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| Chapter 2: Fault in digital circuits | 19 - 40 | ||
| Chapter 3: Digital test pattern generation | 43 - 89, 95 - 108 | ||
| Chapter 4: Signatures and self test | 119 - 130, 141 - 153, 191 - 195 | ||
| Chapter 5: Structured DFT techniques | 201 - 285 | ||
| Chapter 6: Test of structured digital circuits and microprocessors | 297 - 371 | ||
| Chapter 9: The economics of test and final overall summary | 477 - 509 | ||
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Flemming Stassen `Problems on Test of Digital Logic' and `Solutions to Problems on ...' |
All problems | ||
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Assignments and Critiques |
Delay Test | 1 - 9 | |
| Partial Scan Design Using IEEE 1149.1 | 1 - 9 | ||
| Design for Test of Embedded Microprocessors | 1 - 9 | ||
| Bridging Fault Modeling and Testing of ICs | 1 - 8 | ||
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Articles and Notes |
J.P. Shen, W. Maly, F. Joel Ferguson Inductive Fault Analysis of MOS IC's IEEE D&T of Computers Vol. 2/12, pp 13-26, December 1985 (Paper 1) | ||
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F. Stassen in Lecture Notes on Test of Digital Logic ID, DTU, January 1992 Test Pattern Generation, pp 3.9-3.19 (Paper 2) Testability Analysis, pp 5.1-5.9 (Paper 8) | |||
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V.S. Iyengar, B.K. Rosen, I. Spillinger Delay Test Generation 1 - Concepts and Coverage Metrics 1988 IEEE International Test Conference September 1988, pp 857-866 (Paper 3) | |||
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V.S. Iyengar, B.K. Rosen, I. Spillinger Delay Test Generation 2 - Algebra and Algorithms 1988 IEEE International Test Conference September 1988, pp 867-876 (Paper 4) | |||
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M. Abramovici, M.A. Breuer and A.D. Friedman in Digital Systems Testing and Testable Design Computer Science Press, 1992 5 Fault Simulation, pp 131-172 (Paper 5) 6.3.1 TG using iterative array models, pp 249 - 262 (Paper 7) 9.9 Some advanced scan concepts, pp 385 - 396 (Paper A5) | |||
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S. Hwang and R. Rajsuman VLSI Testing for High Reliability: Mixing IDDQ and Logic Testing Proceedings IEEE ICVC93, November 1993, 372 - 376 (Paper 6) | |||
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M. Favalli and M. Dalpasso Bridging fault modeling and simulation for deep submicron CMOS ICs IEEE T-CAD-21/8, August 2002, pp 941-953 (Paper 9) | |||
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K. Son Fault Simulation with Parallel Value List Algorithm VLSI Systems Design, December 1985, 6/12, pp 36-43 (Paper 10) | |||
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W. Maly and M. Patyra Design of ICs Applying Built-In Current Testing JETTA-3/4, December 1992, 397 - 406 (Paper 11) | |||
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M. Abramovici, P.R. Menon, and D.T. Miller Critical Path Tracing - An Alternative to Fault Simulation IEEE D&T of Computers, Vol. 1/1, pp 83-93, February 1984 (Paper 12) | |||
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S.B. Akers, B. Krishnamurthy, S. Park and A. Swaminathan Why is Less Information from Logic Simulation more Useful in Fault Simulation? Proceedings IEEE International Test Conference, Washington DC, 1990, 786 - 800 (Paper 13) | |||
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S. Sheng and M.S. Hsiao Efficient Sequential Test Generation Based on Logic Simulation IEEE D&T of Computers, Vol. 19/5, pp 56-64, September 2002 (Paper 14) | |||
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O.F. Haberl, H.-J. Wunderlich The Synthesis of Self-Test Control Logic Proceedings CompEuro '89, May 1989, pp 5.134-5.136 (Paper 15) | |||
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K. Wilken and J.P. Shen Continuous signature monitoring: low-cost concurrent detection of processor control errors in Dependable Computing for Critical Applications, A. Avizienis and J.C. Laprie (editors) Springer-Verlag 1991, 365 - 384 (Paper 16) | |||
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A. Chandra and K. Chakrabarty Test resource partitioning for SOCs IEEE Design & Test of Computers, Vol. 18/5, pp 80-91, September 2001 (Paper 17) | |||
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A. Benso, S. Chiusano, G. di Natale, P. Prinetto and M.L. Bondoni Online and Offline BIST in IP-Core Design IEEE D&T of Computers, Vol.18/5, November 2001, 92 - 98 (Paper 18) | |||
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R.K. Roy, T.M. Niermann, J.H. Patel, J.A. Abraham, and R.A. Saleh Compaction of ATPG-generated test sequences for sequential circuits IEEE ICCAD-88, Santa Clara, November 1988, pp 382-385 (Paper 19) | |||
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P. Girard Survey of low-power testing of VLSI circuits IEEE D&T of Computers, Vol. 19/3, pp 82-92, May 2002 (Paper 20) | |||
