We present TSNBench, the first benchmark for evaluating large language model (LLM) proficiency in Time-Sensitive Networking (TSN), a suite of IEEE 802.1 standards for deterministic communication with bounded latency in safety-critical domains such as autonomous vehicles, aviation, defense, and industrial automation. While LLMs have been extensively evaluated on general knowledge tasks, their capabilities in safety-critical networking domains remain largely unexplored. TSNBench comprises 939 expert-validated multiple-choice questions (MCQs) covering diverse TSN mechanisms, along with 100 open-ended Worst-Case Delay (WCD) computation tasks for Credit-Based Shaper (CBS) and Cyclic Queuing and Forwarding (CQF) across varying network topologies and traffic conditions. MCQ answers are validated by domain experts, and open-ended ground truth WCD values are computed using a verified Network Calculus (NC) solver for CBS and closed-form mathematical upper bounds for CQF. We evaluate 16 LLMs and find that although models achieve 67 to 95% accuracy on MCQs, they fail substantially on open-ended WCD computation. For CBS, only GPT-5 achieves a Mean Absolute Percentage Error (MAPE) of 36.2%, meaning its predicted WCD deviates by 36.2% of the actual TSN flow delay on average, while most models exceed 80%. For CQF, the best model achieves 41.8% MAPE, with most models clustering between 80% and 100%. Such errors are large relative to TSN latency budgets and can lead to violations of real-time constraints and unsafe configurations. TSNBench demonstrates that MCQ benchmarks may overestimate LLM capabilities in safety-critical networking domains.

@article{Debnath:2026aa,
  author = {Debnath, Rubi and Mateu, Daniel Bujosa and Zhao, Luxi and Craciunas, Silviu S. and Pop, Paul and Steinhorst, Sebastian},
  title = {TSNBench: Benchmarking LLM Proficiency in Time-Sensitive Networking},
  year = {2026},
  url = {http://arxiv.org/abs/2605.09481v1}
}

Modern automotive software architectures comprise large sets of mixed-criticality functions executing on shared multi-core platforms with strict real-time and end-to-end timing requirements. Sensor-to-actuator data propagation in such systems is typically expressed via cause-effect chains with worst-case data-age budgets. Job-level dependencies (JLDs) have been introduced to provide a schedule-agnostic mechanism for bounding the data age independently of the underlying scheduler. The state-of-the-art methods for synthesizing JLDs, however, do not check whether the produced JLDs are enforceable under a concrete scheduling policy or jointly schedulable at the system level. In this paper we propose the first machine-learning-based JLD synthesis method, built around a two-level Graph Neural Network with temperature-controlled sampling that learns the structural patterns connecting cause-effect chain configurations to their JLD solutions. Since learned outputs may not be correct by construction, we embed the GNN in a novel Generate-and-Verify architecture in which a safe DP data-age checker, together with a per-chain EDF feasibility checker and a system-level demand-bound test, accept or reject each candidate. We show that the ML-based generator substantially outperforms the original greedy heuristic while achieving orders-of-magnitude lower synthesis time, demonstrating that learned structural priors can effectively replace exponential propagation-tree enumeration on this class of real-time scheduling problems.

@article{Craciunas:2026aa,
  author = {Craciunas, Silviu S. and Hakert, Christian and Chen, Jian-Jia and Hanzálek, Zdeněk and Pop, Paul},
  title = {Schedulable Job-Level Dependencies for Cause-Effect Chains via Graph Neural Networks},
  year = {2026},
  url = {http://arxiv.org/abs/2607.02624v1}
}

Time-Sensitive Networking (TSN) provides deterministic guarantees and bounded latency for safety-critical applications across different domains. While the IEEE 802.1 TSN standards provide a comprehensive set of mechanisms for time synchronization, shaping, scheduling, resource reservation, and reliability, deploying TSN in real-world applications remains a complex, multi-step engineering task. Existing research primarily focuses on optimizing individual objectives, such as increasing schedulability, reducing latency, accelerating solution generation, or improving performance analysis. However, whether these extensively researched solutions can be deployed in real-world systems remains unanswered, as the assumptions made in these methodologies often differ from practical hardware constraints. Therefore, a broader, holistic view of end-to-end TSN deployment and management remains an open research question. Currently, there is a lack of a unified perspective, consensus, and coordinated research efforts focusing on a comprehensive end-to-end TSN deployment workflow. We present a comprehensive overview of the TSN deployment lifecycle, current challenges, limitations of existing tools, and future research directions for TSN deployment and management. Lastly, we identify key research gaps from a deployment perspective and provide guidance for the development of next-generation deployable TSN networks.

@article{Debnath:2026ab,
  author = {Debnath, Rubi and Pop, Paul and Craciunas, Silviu S. and Boyer, Marc and Steinhorst, Sebastian},
  title = {Making Time-Sensitive Networking Deployable: A Comprehensive Lifecycle Architecture},
  year = {2026},
  url = {http://arxiv.org/abs/2608.20500v1}
}

@misc{Craciunas:2026ab,
  author = {Craciunas, Silviu S. and Becker, Matthias and Pop, Paul},
  title = {Automotive Cause-Effect Chains in the Wild: A Real-World Industrial Benchmark and Generator},
  publisher = {Zenodo},
  year = {2026},
  doi = {10.5281/zenodo.20637979},
  url = {https://doi.org/10.5281/zenodo.20637979}
}

Time-Sensitive Networking (TSN) is a foundational technology for deterministic communication in industrial automation, automotive and aerospace applications. However, its complexity increases significantly when handling heterogeneous traffic with multiple shaping mechanisms and when networks span multiple administrative domains. This paper presents a targeted state-of-the-art review of analysis and optimisation methods for such multishaper and multidomain TSN systems. We selected representative works through keyword searches on scholarly databases and expert-driven citation analysis, focusing on papers that directly contribute analysis or optimisation methods for these configurations. This review examines four multishaper combinations, that is, time-aware shaper (TAS) with credit-based shaper (CBS), asynchronous traffic shaper (ATS), cyclic queueing and forwarding (CQF) and frame pre-emption (FP), and four multidomain scenarios, that is, TSN-to-TSN federation, TSN-to-Deterministic Networking (DetNet) integration, TSN-to-5G and TSN-to-Wi-Fi convergence. We synthesise 44 representative works in two comparative tables that categorise each study by analysis method, optimisation approach, configuration scope and validation scale. Based on the review and experimental evidence, we summarise 14 open challenge categories across multishaper and multidomain configurations, including the scalability of formal analysis methods, the impact of hardware constraints and the need for unified runtime configuration. Case studies further show that formal analyses become impractical inside large optimisation loops, that joint multishaper optimisation is necessary to avoid infeasible configurations and that large-scale multidomain orchestration remains computationally expensive. We outline future research directions to address these gaps for next-generation industrial systems.

@article{Gavrilut:2026aa,
  author = {Voica Gavrilu{\c t} and Paul Pop},
  title = {Analysis and Optimisation of Multishaper Multidomain Time‐Sensitive Networks: State‐of‐the‐Art and Open Challenges},
  journal = {IET Cyber-Physical Systems: Theory and Applications},
  publisher = {John Wiley \& Sons Inc.},
  year = {2026},
  doi = {10.1049/cps2.70057}
}

Time-Sensitive Networks (TSN) are designed to ensure real-time and reliability performance in industrial applications. While Integer Linear Programming (ILP) based scheduling methods can achieve optimal solutions for network design, they face scalability issues and are primarily suitable for small-scale problems. This paper presents a group scheduling strategy targeting for large-scale TSN applications. The traffic dependency is modeled as an undirected graph to reveal the naturally existing intrinsic community structure among flows. Critical flows and intra-group flows are explicitly identified, allowing the scheduling problem to be decomposed into several subset scheduling problems. The scheduling process prioritizes critical flows, while intra-group flows are scheduled in parallel. Experimental evaluations confirm that the proposed method significantly reduces flowspan and computational overhead, offering an efficient and scalable solution for large scale industrial TSN applications.

@inproceedings{Zhang:2025aa,
  author = {Lei Zhang and Wending Wang and Paul Pop},
  title = {Modularity-Driven Group Scheduling for Time-Sensitive Networks},
  booktitle = {Proceedings of the 2025 IEEE 21st International Conference on Factory Communication Systems (WFCS)},
  publisher = {IEEE},
  year = {2025},
  doi = {10.1109/WFCS63373.2025.11077646}
}

HiPEAC Vision 2025 outlines a long-term outlook for computing, emphasizing the NCP's role in AI, innovative hardware, and sustainability, while analyzing Europe's position in global technological races.

@techreport{Mackay:2025aa,
  author = {Adam Mackay and Alessandra Bagnato and Luz, {Carles Hern{\'a}ndez} and Claudio Pastrone and Claudio Sassanelli and Djamila Aouada and Macedo, {Hugo Daniel} and Marcus V{\"o}lp and Michael Henshaw and Mikl{\'o}s Gy{\"o}rffi and Paul Pop and Larsen, {Peter Gorm} and Peter Popov and Rajendra Akerkar and Takaghaj, {Sanaz Mahmoodi} and Thorsten Weyer and Michael O{\textquoteright}Boyle and Randy Allen and Eduard Ayguad{\'e} and Ulises Cort{\'e}s and Manuel Arenaz},
  title = {HiPEAC Vision 2025: High Performance, Edge and Cloud Computing},
  year = {2025}
}

Microfluidic biochips are replacing the conventional biochemical analysers integrating the necessary functions on-chip. We are interested in Flow-Based Microfluidic Biochips (FBMB), where a continuous flow of liquid is manipulated using integrated microvalves. Using microvalves and channels, more complex Fluidic Units (FUs) such as switches, micropumps, mixers and separators can be constructed. When running a biochemical application on a FBMB, fluid volumes are dispensed from input reservoirs and used by the FUs. Given a biochemical application and a biochip, one of the key problems which we are discussing in this paper, is in determining the fluid volume assignment for each operation of the application, such that the FUs' volume requirements are satisfied, while over- and underflow are avoided and the total volume of fluid used is minimized. We illustrate the main problems using examples, and provide a review of related work on volume management. We present algorithms for optimizing fluid volume assignments and for reusing leftover fluids to reduce waste. This also includes the optimization of mixing operations which significantly impact the required fluid volumes. We identify the main challenges related to volume management and discuss possible solutions. Finally we compare the outcome of volume management using fixed- and arbitrary-ratio mixing technology, demonstrating significant reductions in fluid consumption for real biochemical assays.

@article{Schneider:2025aa,
  author = {Schneider, Alexander and Madsen, Jan and Pop, Paul},
  title = {Fluid Volume Assignment for Flow-Based Biochips: State-of-the-Art and Research Challenges},
  year = {2025},
  url = {http://arxiv.org/abs/2505.03540v1}
}

Cyber-Physical Systems (CPS) research continues support across many contributing technology domains as a facilitator for their integration into domains like transport, health, manufacturing and space. The Next Computing Paradigm will play a key supporting role for future CPS research, providing an established alignment of enabling technologies around computing. Meanwhile, there is a need to look at research that eases the complexity of traversing the research itself and raising awareness that this work opens the markets for contributing European technology fields.

@techreport{Robinson:2025ab,
  author = {Robinson, {Charles R.} and Rajendra Akerkar and Djamila Aouada and Alessandra Bagnato and Mikl{\'o}s Gy{\"o}rffi and Michael Henshaw and Larsen, {Peter Gorm} and Luz, {Carles Hernandez} and Macedo, {Hugo Daniel} and Adam Mackay and Claudio Pastrone and Paul Pop and Claudio Sassanelli and Marcus V{\"o}lp and Thorsten Weyer},
  title = {Extended Recommendations for Advances on Cyber-Physical Systems: A white paper in relation to the HiPEAC Vision 2025},
  publisher = {Zenodo},
  year = {2025},
  doi = {10.5281/zenodo.14624958}
}

Cyber-physical Systems, supported by the Next Computing Paradigm, will draw upon the continued research integration advances for the development of future large-scale safety-critical systems, involving many technology and influencer domains. Novel approaches and tools will be required to tackle the increasingly multi-dimensional challenges between the communities to benefit these future systems, especially their adaptability to new technologies.

@techreport{Robinson:2025aa,
  author = {Charles Robinson and Rajendra Akerkar and Djamila Aouada and Alessandra Bagnato and Mikl{\'o}s Gy{\"o}rffi and Michael Henshaw and Larsen, {Peter Gorm} and Luz, {Carles Hernandez} and Macedo, {Hugo Daniel} and Adam Mackay and Claudio Pastrone and Peter Popov and Paul Pop and Claudio Sassanelli and Marcus V{\"o}lp and Thorsten Weyer},
  title = {Bridging the Stakeholder Domains that Produce Cyber-physical Systems: A white paper in relation to the HiPEAC Vision 2025},
  publisher = {Zenodo},
  year = {2025},
  doi = {10.5281/zenodo.14693254}
}

IEEE 802.1 Time-Sensitive Networking (TSN) has proposed several shapers, for example, time-aware shaper (TAS, 802.1Qbv), asynchronous traffic shaping (ATS, 802.1Qcr), credit-based shaper (CBS, 802.1Qav), and cyclic queuing and forwarding (CQF, 802.1Qch). The shapers have their advantages and disadvantages and can be used in isolation or in combination to address the varied timing requirements of industrial application streams. There is very limited work on how to analyse and configure shaper combinations. The authors are interested in the configuration optimisation of multi-shaper TSN networks, targeting the TAS + CBS, TAS + ATS, and TAS + Multi-CQF combinations. The authors first propose multi-shaper integration approaches, focusing on a novel iterative delay analysis for TAS + ATS, an approach to integrate TAS and CQF by placing constraints on TAS scheduling as well as the TAS and CBS integration. We formulate the combinatorial optimisation problem of configuring multi-shaper TSN networks, which consists, for example, of the routing of streams, the assignment of streams to the egress port queues, and the synthesis of gate control lists for TAS. Then, the authors propose a solution based on a simulated annealing metaheuristic. The proposed solutions are evaluated on large realistic test cases, up to tens of thousands of streams and devices.

@article{Pop:2024aa,
  author = {Paul Pop and Konstantinos Alexandris and Tongtong Wang},
  title = {Configuration of multi-shaper Time-Sensitive Networking for industrial applications},
  journal = {IET Networks},
  publisher = {John Wiley \& Sons Inc.},
  year = {2024},
  doi = {10.1049/ntw2.12129}
}

Energy storage systems, especially lithium-ion batteries have gained significant attention and interest due to their potential in storing electrical energy and environmental sustainability. They play a crucial role in electric vehicles and significantly impact their performance, particularly in terms of electric driving range and quick acceleration. Despite their advantages, lithium-ion batteries also have limitations. These include the potential for thermal runaway, which can lead to safety hazards if not properly managed, such as outgassing, fire, and explosion that in turn cause significant property damage and fatalities. Published studies on road vehicles have not adequately considered the safety assurance of rechargeable energy storage systems in accordance with ISO 26262 standard. Accordingly in this paper, we focus on the safety assurance of a battery management system (BMS) that prevents thermal runaway and keeps lithium-ion batteries safe in electric vehicles. To this end, the safety life cycle process is performed. At first, the potential hazards that lead to thermal runaway impacting the functions of electric vehicles have been identified and safety goals related to means for preventing and controlling hazards are formulated. Next, the functional safety requirements are derived from each safety goal, and subsequently technical safety requirements are derived. To demonstrate the acceptable safety of electric vehicles using the BMS strategy, the safety cases are developed from the functional safety activities. The safety contracts are derived from battery specifications and chemistry and are associated with safety cases that provide the means for performing necessary adaptations at the operational phase. We leveraged a simulation for performing the verification and validation as well as finetuning of the BMS strategy. Simulation data is gathered, and the critical parameters are monitored to determine safety violations, control actions are triggered to resolve them, and safety cases are updated to reflect the current system safety.

@article{Muram:2024aa,
  author = {Muram, {Faiz Ul} and Paul Pop and Javed, {Muhammad Atif}},
  title = {Assuring the safety of rechargeable energy storage systems in electric vehicles},
  journal = {Journal of Systems Architecture},
  publisher = {Elsevier},
  year = {2024},
  doi = {10.1016/j.sysarc.2024.103218}
}

Fog Computing for Robotics and Industrial Automation, FORA, was a European Training Network which focused on future industrial automation architectures and applications based on an emerging technology, called Fog Computing. The research project focused on research related to Fog Computing with applicability to industrial automation and manufacturing. The main outcome of the FORA project was the development of a deterministic Fog Computing Platform (FCP) to be used for implementing industrial automation and robotics solutions for Industry 4.0. This paper reports on the scientific outcomes of the FORA project. FORA has proposed a reference system architecture for Fog Computing, which was published as an open Architecture Analysis Design Language (AADL) model. The tech-nologies developed in FORA include fog nodes and hypervisors, resource management mechanisms and middleware for deploying scalable Fog Computing applications, while guaranteeing the non-functional properties of the virtualized industrial control applications, and methods and processes for assuring the safety and security of the FCP. Several industrial use cases were used to evaluate the suitability of the FORA FCP for the Industrial IoT area, and to demonstrate how the platform can be used to develop industrial control applications and data analytics applications.

@inproceedings{Barzegaran:2023aa,
  author = {Mohammadreza Barzegaran and Paul Pop},
  title = {The FORA European Training Network on Fog Computing for Robotics and Industrial Automation},
  booktitle = {Proceedings of the 2023 Design, Automation and Test in Europe Conference and Exhibition},
  publisher = {IEEE},
  year = {2023},
  doi = {10.23919/DATE56975.2023.10137067}
}

Time-Sensitive Networks (TSN) aims at providing a solid underpinning for the support of application connectivity demands across a wide spectrum of use cases and operational environments, such as industrial automation and automotive networks. However, handling network updates in TSN entails additional challenges, stemming from the need to perform both flow rerouting and TSN schedule reconfiguration. To address this issue, we propose a software-defined network (SDN)-based approach for low-overhead TSN network updates, exploiting segment routing over IPv6 (SRv6) for path control. To this end, we introduce the concept of TSN subgraphs in order to quickly reschedule the flows traversing the problematic area and propose a TSN-aware routing heuristic to minimize the convergence time. We further describe the control plane implementation and its integration into Mininet, which empowers us to conduct a wide range of performance tests. Our evaluation results indicate that our approach yields faster recovery and reduces significantly the number of required reconfigurations upon failures, at the expense of a small SRv6 encoding/decoding overhead.

@article{Kumar:2023aa,
  author = {{Nandha Kumar}, Gagan and Kostas Katsalis and Panagiotis Papadimitriou and Paul Pop and Georg Carle},
  title = {SRv6-based Time-Sensitive Networks (TSN) with low-overhead rerouting},
  journal = {International Journal of Network Management},
  publisher = {John Wiley and Sons Ltd},
  year = {2023},
  doi = {10.1002/nem.2215}
}

This paper presents an integrative exploration of key digital technologies instrumental in enabling the global green transition. In view of ambitious climate neutrality targets, it underscores the complex interplay between these technologies, policy implications, research challenges, and real-world applications in building a sustainable, low-carbon solutions. From a policy perspective, the paper delves into the systemic opportunities and challenges, providing valuable insights for various stakeholders. The discussion also encompasses pivotal research areas necessitated by the convergence of digital technologies and sustainable practices, emphasizing the need for a multi-disciplinary approach. Further, the paper identifies the practical applications of digital technologies across a range of sectors, highlighting several illustrative case studies, drawing lessons for future implementations. It concludes with forward-looking recommendations, stressing the significance of coherent policy coordination, public engagement, and global cooperation in furthering the digital-led green transition.

@inproceedings{Pop:2023ab,
  author = {Paul Pop and Christian Graulund and Sonia Yeh and Martin T{\"o}rngren},
  title = {Special Session: Digital Technologies for Sustainability{\textemdash}Research Challenges and Opportunities},
  booktitle = {Proceedings of 2023 International Conference on Hardware/Software Codesign and System Synthesis},
  publisher = {IEEE},
  year = {2023},
  doi = {10.1145/3607888.3608960}
}

In order to meet the requirements of critical applications, modern multi-core multi-SoC real-time systems must handle both periodic and sporadic events within specified deadlines. A two-level scheduling hierarchy that combines time-triggered and fixed-priority scheduling is effective for managing periodic time-triggered (TT) and sporadic event-triggered (ET) tasks, respectively. We introduce two polling-based approaches, called simple and advanced polling, for guaranteeing both TT and ET task deadlines within single core systems. We then propose an optimization heuristic for the task-to-core allocation problem based on genetic algorithms for fully partitioned multi-core systems that can be applied to both polling methods. We evaluate the schedulability and runtime performance of the polling approaches and investigate the effectiveness of the allocation heuristic using synthetic test cases based on real-world application characteristics. The results show that both polling approaches achieve high schedulability with low runtime, and the allocation heuristic can generate good solutions for fully partitioned systems. Furthermore, we show that the server design problem of the advanced polling approach can be integrated into the allocation heuristic to achieve better solutions in terms of schedulability and that our choice of the genetic algorithm has a good speedup when being parallelized.

@inproceedings{Meroni:2023aa,
  author = {Carlo Meroni and Craciunas, {Silviu S.} and Ana{\"i}s Finzi and Paul Pop},
  title = {Mapping and Integration of Event- and Time-triggered Real-time Tasks on Partitioned Multi-core Systems},
  booktitle = {Proceedings of the 2023 IEEE 28th International Conference on Emerging Technologies and Factory Automation (ETFA)},
  publisher = {IEEE},
  year = {2023},
  doi = {10.1109/ETFA54631.2023.10275547}
}

@inbook{Pop:2023aa,
  author = {Paul Pop and Martin T{\"o}rngren and Sonia Yeh and Haydn Thompson},
  title = {Digital Technologies for a Sustainable Nordic Future: Challenges, Opportunities, and Policy Implications},
  booktitle = {Fast Track to Vision 2030},
  publisher = {Nordforsk},
  year = {2023}
}

Time-Sensitive Networking (TSN) collectively defines a set of protocols and standard amendments that enhance IEEE 802.1Q Ethernet nodes with time-aware and fault-tolerant capabilities. Specifically, the IEEE 802.1Qbv amendment defines a timed-gate mechanism that governs the real-time transmission of critical traffic via a so-called Gate Control List (GCL) schedule encoded in each TSN-capable network device. Most TSN scheduling mechanisms are designed for homogeneous TSN networks in which all network devices must have at least the TSN capabilities related to scheduled gates and time synchronization. However, this assumption is often unrealistic since many distributed applications use heterogeneous TSN networks with legacy or off-the-shelf end systems that are unscheduled and/or unsynchronized. We propose a new scheduling paradigm for heterogeneous TSN networks that intertwines a network calculus worst-case interference analysis within the scheduling step. Through this, we compromise on the solution’s optimality to be able to support heterogeneous TSN networks featuring unscheduled and/or unsynchronized end-systems while guaranteeing the real-time properties of critical communication. Within this new paradigm, we propose two solutions to solve the problem, one based on a Constraint Programming formulation and one based on a Simulated Annealing metaheuristic, that provide different trade-offs and scalability properties. We compare and evaluate our flexible window-based scheduling methods using both synthetic and real-world test cases, validating the correctness and scalability of our implementation. Furthermore, we use OMNET++ to validate the generated GCL schedules.

@article{Reusch:2023aa,
  author = {Niklas Reusch and Mohammadreza Barzegaran and Luxi Zhao and Craciunas, {Silviu S.} and Paul Pop},
  title = {Configuration optimization for heterogeneous time-sensitive networks},
  journal = {Real-Time Systems},
  publisher = {Springer Netherlands},
  year = {2023},
  doi = {10.1007/s11241-023-09414-0}
}

Time-Sensitive Networks (TSN) enhance standard IEEE 802.1Q Ethernet devices with real-time and time-aware capabilities. The forwarding of time-critical frames is done according to a so-called Gate Control List (GCL) schedule via the timed-gate mechanism introduced in IEEE 802.1Qbv. Most TSN scheduling mechanisms impose that all devices in the network must have the TSN capabilities related to scheduled gates and time synchronization. However, this is often an unrealistic assumption since many distributed applications use heterogeneous TSN networks with legacy or off-the-shelf end systems that are unscheduled and/or unsynchronized. This paper proposes a novel, more flexible TSN scheduling algorithm that intertwines a worst-case delay analysis within the scheduling synthesis step. Through this, we leverage the solution's optimality to support heterogeneous TSN networks featuring unscheduled and/or unsynchronized end-systems while still guaranteeing the timeliness of critical communication. We evaluate the performance of our approach using both synthetic and real-world use cases, comparing it with existing TSN scheduling mechanisms. Furthermore, we use OMNET++ to validate the generated GCL schedules.

@inproceedings{Barzegaran:2022ab,
  author = {Mohammadreza Barzegaran and Niklas Reusch and Luxi Zhao and Craciunas, {Silviu S.} and Paul Pop},
  title = {Real-Time Traffic Guarantees in Heterogeneous Time-sensitive Networks},
  booktitle = {Proceedings of the 30th International Conference on Real-Time Networks and Systems},
  publisher = {Association for Computing Machinery},
  year = {2022},
  doi = {10.1145/3534879.3534921},
  url = {https://rtns2022.inria.fr/}
}

Owning to the sub-standards being developed by IEEE Time-Sensitive Networking (TSN) Task Group, the traditional IEEE 802.1 Ethernet is enhanced to support real-time dependable communications for future time-and safety-critical applications. Several sub-standards have been recently proposed that introduce various traffic shapers (e.g., Time-Aware Shaper (TAS), Asynchronous Traffic Shaper (ATS), Credit-Based Shaper (CBS), Strict Priority (SP)) for flow control mechanisms of queuing and scheduling, targeting different application requirements. These shapers can be used in isolation or combination and there is limited work that analyzes, evaluates, and compares their performance, which makes it challenging for end-users to choose the right combination for their applications. This paper aims at (i) quantitatively comparing various traffic shapers and their combinations, (ii) summarizing, classifying, and extending the architectures of individual and combined traffic shapers and their Network calculus (NC)-based performance analysis methods, and (iii) filling the gap in the timing analysis research on handling ATS and CBS used for different priority queues, and two novel hybrid architectures of combined traffic shapers, i.e., TAS+ATS+SP and TAS+ATS+CBS when ATS and CBS used at the same queue. A large number of experiments, using both synthetic and realistic test cases, are carried out for quantitative performance comparisons of various individual and combined traffic shapers, from the perspective of upper bounds of delay, backlog, and jitter. To the best of our knowledge, we are the first to quantitatively compare the performance of the main traffic shapers in TSN. The paper aims at supporting the researchers and practitioners in the selection of suitable TSN sub-protocols for their use cases.

@article{Zhao:2022aa,
  author = {Luxi Zhao and Paul Pop and Sebastian Steinhorst},
  title = {Quantitative Performance Comparison of Various Traffic Shapers in Time-Sensitive Networking},
  journal = {IEEE Transactions on Network and Service Management},
  publisher = {Institute of Electrical and Electronics Engineers Inc.},
  year = {2022},
  doi = {10.1109/TNSM.2022.3180160}
}

Industrie 4.0 reinforces advanced technology development to realize Time-Sensitive Networking (TSN) with real-time guarantees. The evolution of traditional industrial- automation systems such as Programmable Logic Controllers (PLCs) to cyber-physical systems by means of virtualization is one of the key enhancements. In this paper, we evaluate the impact of the placement of virtual PLCs (vPLCs) at edge clouds in conjunction with scheduling and routing of Time-Triggered (TT) traffic in 802.1Qbv-based industrial networks. We propose two approaches to solve this problem adopting a multi-objective optimization model. In the first approach, we solve separately the problem of placement and scheduling-routing by using a Mixed Integer Linear Programming (MILP) formulation. While in the second approach, we propose a Simulated Annealing (SA)- based meta-heuristic to solve the joint placement, scheduling, and routing optimization problem. We compare both the algorithms for real-world test cases and validate our solutions using the OMNeT++ simulator.

@inproceedings{Bhattacharjee:2022aa,
  author = {Sushmit Bhattacharjee and Konstantinos Alexandris and Emil Hansen and Paul Pop and Thomas Bauschert},
  title = {Latency-Aware Function Placement, Routing, and Scheduling in TSN-based Industrial Networks},
  booktitle = {Proceedings of 2022 IEEE International Conference on Communications},
  publisher = {IEEE},
  year = {2022},
  doi = {10.1109/ICC45855.2022.9839028},
  url = {https://icc2022.ieee-icc.org/}
}

In this paper, we consider that critical control applications and Fog applications share a Fog Computing Platform (FCP). Critical control applications are implemented as periodic hard real-time tasks and messages and have stringent timing and safety requirements, and require safety certification. Fog applications are implemented as aperiodic tasks and messages and are not critical. Such applications need different approaches to guarantee their timing and dependability requirements. We formulate an optimization problem for the joint configuration of critical control and Fog applications, such that (i) the deadlines and Quality-of-Control (QoC) of control applications are guaranteed at design-time, (ii) the configuration is extensible and supports the addition of future new control applications without requiring costly re-certification, and (iii) the design-time configuration together with the runtime Fog resource management mechanisms, can successfully accommodate multiple dynamic responsive Fog applications. We evaluate our approach on several test cases assuming scenarios for hosting both Fog applications and future critical control applications. The results show that our approach generates extensible schedules which enables Fog nodes to handle Fog applications with a shorter response time and a larger number of future control applications.

@article{Barzegaran:2022aa,
  author = {Mohammadreza Barzegaran and Paul Pop},
  title = {Extensibility-aware Fog Computing Platform configuration for mixed-criticality applications},
  journal = {Journal of Systems Architecture},
  publisher = {Elsevier},
  year = {2022},
  doi = {10.1016/j.sysarc.2022.102776}
}

Time-Sensitive Networking (TSN) extends IEEE 802.1 Ethernet for safety-critical and real-time applications in several areas, for example, automotive, aerospace or industrial automation. However, many of these systems also have stringent security requirements, and security attacks may impair safety. Given a TSN-based distributed architecture, a set of applications with tasks and messages as well as a set of security and redundancy requirements, the authors are interested to synthesise a system configuration such that the real-time, safety and security requirements are upheld. The Timed Efficient Stream Loss-Tolerant Authentication (TESLA) low-resource multicast authentication protocol is used to guarantee the security requirements and redundant disjunct message routes to tolerate link failures. The authors consider that tasks are dispatched using a static cyclic schedule table and that the messages use the time-sensitive traffic class in TSN, which relies on schedule tables (called Gate Control Lists, GCLs) in the network switches. A configuration consists of the schedule tables for tasks as well as the disjoint routes and GCLs for messages. A Constraint Programing-based formulation, which can be used to find an optimal solution with respect to the cost function, is proposed. Additionally, a Simulated Annealing-based metaheuristic, which can find good solution for large test cases, is proposed. The authors evaluate both approaches on several test cases.

@article{Reusch:2022aa,
  author = {Niklas Reusch and Craciunas, {Silviu S.} and Paul Pop},
  title = {Dependability-aware routing and scheduling for Time-Sensitive Networking},
  journal = {IET Cyber-Physical Systems: Theory and Applications},
  publisher = {John Wiley \& Sons Inc.},
  year = {2022},
  doi = {10.1049/cps2.12030}
}

Modern Advanced Driver-Assistance Systems (ADAS) combine critical real-time and non-critical best-effort tasks and messages onto an integrated multi-core multi-SoC hardware platform. The real-time safety-critical software tasks have complex interdependencies in the form of end-to-end latency chains featuring, e.g., sensing, processing/sensor fusion, and actuating. The underlying real-time operating systems running on top of the multi-core platform use static cyclic scheduling for the software tasks, while the communication backbone is either realized through PCIe or Time-Sensitive Networking (TSN). In this paper, we address the problem of configuring ADAS platforms for automotive applications, which means deciding the mapping of tasks to processing cores and the scheduling of tasks and messages. Time-critical messages are transmitted in a scheduled manner via the timed-gate mechanism described in IEEE 802.1Qbv according to the pre-computed Gate Control List (GCL) schedule. We study the computation of the assignment of tasks to the available platform CPUs/cores, the static schedule tables for the real-time tasks, as well as the GCLs, such that task and message deadlines, as well as end-to-end task chain latencies, are satisfied. This is an intractable combinatorial optimization problem. As the ADAS platforms and applications become increasingly complex, such problems cannot be optimally solved and require problem-specific heuristics or metaheuristics to determine good quality feasible solutions in a reasonable time. We propose two metaheuristic solutions, a Genetic Algorithm (GA) and one based on Simulated Annealing (SA), both creating static schedule tables for tasks by simulating Earliest Deadline First (EDF) dispatching with different task deadlines and offsets. Furthermore, we use a List Scheduling-based heuristic to create the GCLs in platforms featuring a TSN backbone. We evaluate the proposed solution with real-world and synthetic test cases scaled to fit the future requirements of ADAS systems. The results show that our heuristic strategy can find correct solutions that meet the complex timing and dependency constraints at a higher rate than the related work approaches, i.e., the jitter constraints are satisfied in over 6 times more cases, and the task chain constraints are satisfied in 41% more cases on average. Our method scales well with the growing trend of ADAS platforms.

@article{McLean:2022aa,
  author = {McLean, {Shane D.} and {Juul Hansen}, {Emil Alexander} and Paul Pop and Craciunas, {Silviu S.}},
  title = {Configuring ADAS Platforms for Automotive Applications Using Metaheuristics},
  journal = {Frontiers in Robotics and AI},
  publisher = {Frontiers Media S.A.},
  year = {2022},
  doi = {10.3389/frobt.2021.762227}
}

Time-Sensitive Networking (TSN) is a task group of the IEEE 802.1 standardization working group (WG) developing the IEEE 802.1 TSN communication standards. TSN is developing a 'toolbox' of many standards to provide support for enabling the separation of critical and non-critical traffic, the timeliness and dependability, i.e., reliability, fault-tolerance, and security, of critical traffic. In this paper we focus on the Cyclic Queuing and Forwarding (CQF) traffic shapers, such as the original CQF, the Cycle Specified Queuing and Forwarding (CSQF) and an extension of those, the so-called Multi-CQF shaper. We define formally the problem of configuring CQF-based networks. We have developed a Constraint Programming (CP) formulation for Multi-CQF, as well as a Simulated Annealing (SA)-based metaheuristic solution. These solutions can also obtain results for CQF and CSQF, which can be seen as a special case of Multi-CQF. The CQF configuration problem is NP-hard. We evaluate our solutions on several test cases and scenarios. The CP formulation can find optimal solutions for small problem sizes but does not scale for realistic test cases. However, SA is able to handle large test cases and to find good quality solutions, making it suitable for both design-time and runtime network configuration. We also present comprehensive evaluation results comparing the CQF-based variants (CQF, CSQF, Multi-CQF) on industrial use cases, contrast them to the Time Aware Shaper (TAS, 802.1Qbv), and discuss their advantages and disadvantages.

@article{Alexandris:2022aa,
  author = {Konstantinos Alexandris and Paul Pop and Tongtong Wang},
  title = {Configuration and Evaluation of Multi-CQF Shapers in IEEE 802.1 Time-Sensitive Networking (TSN)},
  journal = {IEEE Access},
  publisher = {Institute of Electrical and Electronics Engineers},
  year = {2022},
  doi = {10.1109/ACCESS.2022.3214007}
}

Time Slotted Channel Hopping (TSCH) is a medium access protocol defined in the IEEE 802.15.4 standard which have been proven to be one of the most reliable options when it comes to industrial applications. TSCH has been designed to be utilized in static network topologies. Thus, if an application scenario requires a mobile network topology, TSCH does not perform reliably. In this paper we introduce active connectivity for mobile application scenarios, such as mobile robots. This is a feature that enables the option to regulate physical characteristics such as the speed of a node as it moves, in order to keep being connected to the TSCH network. We model the active connectivity approach through a basic example where two nodes are moving towards the same direction to infer the main principles of the introduced approach. We evaluate the active connectivity feature through simulations and quantify trade-off between connectivity and application-layer performance.

@inproceedings{Orfanidis:2022aa,
  author = {Charalampos Orfanidis and Paul Pop and Xenofon Fafoutis},
  title = {Active Connectivity Fundamentals for TSCH Networks of Mobile Robots},
  booktitle = {Proceedings of the 18th Annual International Conference on Distributed Computing in Sensor Systems},
  publisher = {IEEE},
  year = {2022},
  doi = {10.1109/DCOSS54816.2022.00042},
  url = {https://dcoss.org/}
}

Time Slotted Channel Hopping (TSCH) is a medium access protocol defined in the IEEE 802.15.4 standard. It has been demonstrated to be one of the most reliable options when it comes to industrial applications. TSCH offers a degree of large flexibility and can be tailored to the requirements of specific applications. Several performance aspects of TSCH have been investigated so far, such as the energy consumption, the reliability, scalability and many more. However, mobility in TSCH networks remains an aspect that has not been thoroughly explored. In this paper we examine how TSCH performs under mobility situations. We define two mobile scenarios: one where autonomous agriculture vehicles move on a predefined trail, and a warehouse logistics scenario, where autonomous robots/vehicles and workers move randomly. We examine how different TSCH scheduling approaches perform on these mobility patterns and when different number of nodes are operating. The results show that the current TSCH scheduling approaches are not able to handle mobile scenarios efficiently. Moreover, the results provide insights on how TSCH scheduling can be improved for mobile applications.

@article{Orfanidis:2021aa,
  author = {Charalampos Orfanidis and Atis Elsts and Paul Pop and Xenofon Fafoutis},
  title = {TSCH Evaluation under heterogeneous Mobile Scenarios},
  journal = {IoT },
  publisher = {Multidisciplinary Digital Publishing Institute (MDPI)},
  year = {2021},
  doi = {10.3390/iot2040033}
}

Industry 4.0 will only become a reality through the convergence of Operational and Information Technologies (OT & IT), which use different computation and communication technologies. Cloud Computing cannot be used for OT involving industrial applications, since it cannot guarantee stringent non-functional requirements, e.g., dependability, trustworthiness and timeliness. Instead, a new computing paradigm, called Fog Computing, is envisioned as an architectural means to realize the IT/OT convergence. In this paper we propose a Fog Computing Platform (FCP) reference architecture targeting Industrial IoT applications. The FCP is based on: deterministic virtualization that reduces the effort required for safety and security assurance; middleware for supporting both critical control and dynamic Fog applications; deterministic networking and interoperability, using open standards such as IEEE 802.1 Time-Sensitive Networking (TSN) and OPC Unified Architecture (OPC UA); mechanisms for resource management and orchestration; and services for security, fault tolerance and distributed machine learning. We propose a methodology for the definition and the evaluation of the reference architecture. We use the Architecture Analysis Design Language (AADL) to model the FCP reference architecture, and a set of industrial use cases to evaluate its suitability for the Industrial IoT area.

@article{Pop:2021ab,
  author = {Paul Pop and Bahram Zarrin and Mohammadreza Barzegaran and Stefan Schulte and Sasikumar Punnekkat and Jan Ruh and Wilfried Steiner},
  title = {The FORA Fog Computing Platform for Industrial IoT},
  journal = {Information Systems},
  publisher = {Elsevier},
  year = {2021},
  doi = {10.1016/j.is.2021.101727}
}

Edge Computing Platforms (ECP) increasingly integrate applications with mixed-criticality requirements. In this paper, we consider that critical applications and Edge applications share an ECP. Critical applications are implemented as periodic hard real-time tasks and messages and have stringent timing and security requirements. Edge applications are implemented as aperiodic tasks and messages, and are not critical. We assume that the critical tasks are scheduled using static cyclic scheduling, Time-Sensitive Networking (TSN) is used for dependable communication, and Remote Attestation (RA) is employed to check that the platform components are secure. We formulate an optimization problem for the joint scheduling of critical and Edge applications, such that (i) the deadlines of the critical applications are guaranteed at design-time, (ii) the platform has resources to perform RA, and (iii) we can successfully accommodate multiple dynamic responsive Edge applications at runtime. We evaluate our approach on a realistic use case. The results show that our approach generates dependable schedules that can meet the timing constraints of the critical applications, have enough periodic slack to perform RA for security, and can accommodate Edge applications with a shorter response time.

@inproceedings{Reusch:2021aa,
  author = {Niklas Reusch and Paul Pop},
  title = {Scheduling Real-Time Applications on Edge Computing Platforms with Remote Attestation for Security},
  booktitle = {Proceedings of 2021 IEEE/ACM Symposium on Edge Computing},
  publisher = {IEEE},
  year = {2021},
  doi = {10.1145/3453142.3493510}
}

The Nordic Industrial IoT (IIoT) Roadmap has been developed by five Nordic universities to complement existing roadmaps and research agendas, such as the European initiatives on Green Deal, Smart Everything Anywhere, and Autonomous systems—see the section “Related roadmaps & agendas”. A long-term focus on sustainability has provided the Nordic countries with significant advantages. For example, the CO2 intensity (gCO2/KWh) of power and district heating production amounts to only 14% of the EU25 average and transport’s total energy use decreased by over 20% compared with 2000, despite a 70% increase in overall passenger and freight activity. Many of these results have been achieved by a long-term focus on digitalization—in fact the four Nordic countries are ranked on the top four places in EU’s 2020 “Digital Economy and Society Index”. Thus, the Nordic countries are good at both sustainability and digitalization! The Nordic countries are also strong in trustworthiness and cyber-physical systems. We believe that there is now a unique opportunity to leverage these competences (trustworthiness, digitalization—AI, 5G, cloud and edge computing, and the IoT—and CPS) to enable and promote sustainability and a circular economy. However, this requires a much stronger emphasis on multidisciplinary research, networking and testbeds to establish the collaboration and new methodologies and technologies needed for a humancentered and sustainable future. The Nordic IIoT Roadmap outlines several research areas where progress is needed to enable these directions. Examples include: Automated driving for sustainable mobility & transport, Selfpowering systems for IoT & energyefficient sensor networks, Safety, security, and privacy by design, Reduction of the energy consumption of HPC and datacenters and wearables for healthcare and wellbeing. Several private and governmental R&D programs are supporting this Nordic longterm transition, with contributions of more than 100 MEUR per year. The Nordic network demonstrates the value of multidisciplinary collaboration to stimulate research that deals with sustainability challenges and leverages digitalization to provide solutions. However, the complexity of the challenges and the resulting interconnected & smart cyber-physical systems-of-systems is growing, involving more stakeholders, and forming new innovation ecosystems, necessitating further action. To maintain and strengthen the Nordic leading position, we recommend establishing a joint Nordic Center doing research in trustworthy methodologies for the implementation of sustainable IIoT, and specific actions for training the next generation of students in both digitalization and the green transition.

@book{Pop:2021aa,
  title = {Nordic Industrial IoT Roadmap: Research And Innovation For The Green Transition},
  year = {2021}
}

Time-sensitive networking (TSN) is a set of amendments that extend Ethernet to support distributed safety-critical and real-time applications in the industrial automation, aerospace, and automotive areas. TSN integrates multiple traffic types and supports interactions in several combinations. In this article, we consider the configuration supporting scheduled traffic (ST) based on gate-control lists, audio-video bridging (AVB) traffic according to IEEE 802.1BA that has bounded latencies, and best-effort traffic, for which no guarantees are provided. This article extends the timing analysis method to multiple AVB classes and proofs the credit bounds for multiple classes of AVB traffic, respectively, under frozen and nonfrozen behaviors of credit during guard band (GB). They are prerequisites for nonoverflow credits of credit-based shaper (CBS) and preventing starvation of AVB traffic. Moreover, this article proposes an improved timing analysis method reducing the pessimism for the worst-case end-to-end delays of AVB traffic by considering the limitations from the physical link rate and the output of CBS. Finally, we evaluate the improved analysis method on both synthetic and real-world test cases, showing the significant reduction of pessimism on latency bounds compared to related work and presenting the correctness validation compared with simulation results. We also compare the AVB latency bounds in the case of frozen and nonfrozen credit during GB. Additionally, we evaluate the scalability of our method with variation of the load of ST flows and of the bandwidth reservation for AVB traffic.

@article{Zhao:2021ab,
  author = {Luxi Zhao and Paul Pop and Zhong Zheng and Hugo Daigmorte and Marc Boyer},
  title = {Latency Analysis of Multiple Classes of AVB Traffic in TSN with Standard Credit Behavior Using Network Calculus},
  journal = {IEEE Transactions on Industrial Electronics},
  publisher = {Institute of Electrical and Electronics Engineers Inc.},
  year = {2021},
  doi = {10.1109/TIE.2020.3021638}
}

Time-Sensitive Networking (TSN) is an upcoming set of Ethernet standards designed for real-time and safety-critical Internet of Things (IoT) applications in automotive, aerospace and industrial automation domains. With the combination, complexity and flexibility of flow control mechanisms in TSN connected systems, the performance analysis for mixed-critical messages is becoming a difficult challenge. The flexible window-based Gate Control List (GCL) scheduling model has been proposed as a relaxation to assumptions on frames-to-window allocation, mutually exclusive gates opening, and scheduled end systems and switches, which offers more flexibility in the configuration of GCLs. In this paper, we are interested in providing a reliable verification method based on the network calculus theory to drive GCL configurations for TSN networks. To the best of our knowledge, this is the first performance analysis method suitable for the general flexible window-based GCLs in entire TSN networks, by reflecting the relative positional relationships of windows for same priority queues on consecutive nodes and constructing the window limitations into the shaper curve, in order to reduce the pessimism of the latency bounds. We validate the proposed method through Industrial IoT synthetics test cases and two large realistic cases, showing the significant reduction in pessimism on delay bounds, and the correctness and scalability by comparing with results from the previous work and simulation results.

@article{Zhao:2021aa,
  author = {Luxi Zhao and Paul Pop and Zijie Gong and Bingwu Fang},
  title = {Improving Latency Analysis for Flexible Window-Based GCL Scheduling in TSN Networks by Integration of Consecutive Nodes Offsets},
  journal = {IEEE Internet of Things Journal},
  publisher = {Institute of Electrical and Electronics Engineers Inc.},
  year = {2021},
  doi = {10.1109/JIOT.2020.3031932}
}

We propose a Software-Defined Network (SDN)based approach for ultra-fast recovery of Time Sensitive Networks (TSN) in the case of failure events. We exploit the Source Routing paradigm for explicit path control and the creation of a stateless TSN data plane. We further propose a TSN failure recovery routing heuristic used to minimise link congestion, while we also introduce the concept of TSN subgraphs to quickly reschedule the flows traversing the problematic area. We evaluate our approach using SDN-based Source Routing and Linux-based TSN scheduling integrated into Mininet.

@inproceedings{Kumar:2021aa,
  author = {Kumar, {Gagan Nandha} and Kostas Katsalis and Panagiotis Papadimitriou and Paul Pop and Georg Carle},
  title = {Failure Handling for Time-Sensitive Networks using SDN and Source Routing},
  booktitle = {Proceedings of 2021 IEEE 7th International Conference on Network Softwarization},
  publisher = {IEEE},
  year = {2021},
  doi = {10.1109/NetSoft51509.2021.9492666},
  url = {https://netsoft2021.ieee-netsoft.org/}
}

Electric drives, which are a main component in industrial applications, control electric motors and record vital information about their respective industrial processes. The development of electric drives as Fog nodes within a fog computing platform (FCP) leads to new abilities such as programmability, analytics, and connectivity, increasing their value. In this study, the FORA FCP reference architecture is used to implement electric drives as Fog nodes, which is called “fogification”. The fogified drive architecture and its components are designed using Architecture Analysis and Design Language (AADL). The design process was driven by the high-level requirements that the authors elicited. Both the fogified drive architecture and the current drive architecture are used to implement a self baggage drop system in which electric drives are the key components. The fog-based design was then evaluated using several key performance indicators (KPIs), which reveal its advantages over the current drive architecture. The evaluation results show that safety-related isolation is enabled with only 9% overhead on the total Fog node utilization, control applications are virtualized with zero input–output jitter, the hardware cost is reduced by 44%, and machine learning at the edge is performed without interrupting the main drive functionalities and with an average 85% accuracy. The conclusion is that the fog-based design can successfully implement the required electric drive functionalities and can also enable innovative uses needed for realizing the vision of Industry 4.0.

@article{Barzegaran:2021ab,
  author = {Mohammadreza Barzegaran and Nitin Desai and Jia Qian and Paul Pop},
  title = {Electric drives as fog nodes in a fog computing‐based industrial use case},
  journal = {The Journal of Engineering},
  publisher = {John Wiley and Sons Ltd},
  year = {2021},
  doi = {10.1049/tje2.12069}
}

Flow-based microfluidic biochips have attracted much attention in the EDA community due to their miniaturized size and execution efficiency. Previous research, however, still follows the traditional computing model with a dedicated storage unit, which actually becomes a bottleneck of the performance of biochips. In this paper, we propose a distributed channel-storage architecture (DCSA) to cache fluid samples inside flow channels temporarily. Since distributed storage can be accessed more efficiently than a dedicated storage unit and channels can switch between the roles of transportation and storage easily, biochips with this architecture can achieve a higher execution efficiency even with fewer resources. Furthermore, we also address the flow-path planning that enables the manipulation of actual fluid transportation/caching on a chip. Simulation results confirm that the execution efficiency of a bioassay can be improved significantly, while the number of valves in the biochip can be reduced accordingly. Also, flow paths for transportation tasks can be constructed and planned automatically with minimum extra resources.

@article{Liu:2021aa,
  author = {Chunfeng Liu and Xing Huang and Bing Li and Hailong Yao and Paul Pop and Tsung-Yi Ho and Ulf Schlichtmann},
  title = {DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  publisher = {Institute of Electrical and Electronics Engineers Inc.},
  year = {2021},
  doi = {10.1109/TCAD.2020.2994267}
}

In this paper we are interested in real-time control applications that are implemented using Fog Computing Platforms consisting of interconnected heterogeneous Fog Nodes (FNs). Similar to previous research and ongoing standardization efforts, we assume that the communication between FNs is achieved via the IEEE 802.1 Time Sensitive Networking (TSN) standard. We model the control applications as a set of real-time flows, and we assume that the messages are transmitted using scheduled traffic that is using the Gate Control Lists (GCLs) in TSN. Given a network topology and a set of control applications, we are interested to synthesize the GCLs for messages such that the Quality-of-Control (QoC) of control applications is maximized and the deadlines of real-time messages are satisfied. We have proposed a Constraint Programming (CP)-based solution to this problem, and developed an accurate analytical model for QoC, which, together with a metaheuristic search employed in the CP solver can drive the search quickly towards good quality solutions. We have evaluated the proposed strategy on several test cases including realistic test cases and also validate the resulted GCLs on a TSN hardware platform and via simulations in OMNET++.

@article{Barzegaran:2021aa,
  author = {Mohammadreza Barzegaran and Paul Pop},
  title = {Communication Scheduling for Control Performance in TSN-based Fog Computing Platforms},
  journal = {IEEE Access},
  publisher = {Institute of Electrical and Electronics Engineers},
  year = {2021},
  doi = {10.1109/ACCESS.2021.3069142}
}

Time-Sensitive Networking (TSN) extends IEEE 802.1 Ethernet for safety-critical and real-time applications in several areas, e.g., automotive, aerospace or industrial automation. However, many of these systems also have stringent security requirements, and security attacks may impair safety. Given a TSN-based distributed architecture, a set of applications with tasks and messages, as well as a set of security and redundancy requirements, we are interested to synthesize a system configuration such that the real-time, safety and security requirements are satisfied. We use the Timed Efficient Stream Loss-Tolerant Authentication (TESLA) low-resource multicast authentication protocol to guarantee the security requirements, and redundant disjunct message routes to tolerate link failures. We consider that the tasks are scheduled using static cyclic scheduling and that the messages use the time-sensitive traffic class in TSN, which relies on schedule tables (called Gate Control Lists, GCLs) in the network switches. A configuration consists of the schedule tables for tasks as well as the disjoint routes and GCLs for messages. We propose a Constraint Programming-based formulation for this problem and we evaluate it on several test cases.

@inproceedings{Reusch:2020ac,
  author = {Niklas Reusch and Paul Pop and Craciunas, {Silviu S.}},
  title = {Work-In-Progress: Safe and Secure Configuration Synthesis for TSN using Constraint Programming},
  booktitle = {Proceedings of IEEE 41st Real-Time Systems Symposium},
  publisher = {IEEE},
  year = {2020},
  doi = {10.1109/RTSS49844.2020.00045}
}

Time-Sensitive Networking (TSN) introduces standardized mechanisms that add real-time capabilities to IEEE 802.1 Ethernet networks. In particular, the Time-Aware Shaper (TAS) can be used to send frames in a deterministic fashion according to a predefined global schedule. Existing methods for generating the global communication schedule enforce isolation either in the time or in the space domain. This extended abstract presents a novel, more flexible window-based scheduling algorithm which removes the previously required isolation constraints for Scheduled Traffic (ST) by integrating worst-case delay analysis to guarantee bounded latency.

@inproceedings{Reusch:2020ab,
  author = {Niklas Reusch and Luxi Zhao and Craciunas, {Silviu S.} and Paul Pop},
  title = {Window-Based Schedule Synthesis for Industrial IEEE 802.1Qbv TSN Networks},
  booktitle = {Proceedings of 16th IEEE International Conference on Factory Communication Systems},
  publisher = {IEEE},
  year = {2020},
  doi = {10.1109/WFCS47810.2020.9114414},
  url = {https://ieeexplore.ieee.org/xpl/conhome/9110481/proceeding}
}

TSNConf is a suite of tools developed at the Technical University of Denmark for the analysis and configuration of IEEE 802.1 Time-Sensitive Networking (TSN) networks for safety- and security-critical applications. TSNConf has several modules that tackle design and analysis tasks, such as, topology design, traffic type selection, routing and scheduling, and timing analysis. However, TSNConf has so far not considered security and redundancy requirements. In this demo we will present TSNConf with a focus on the 3SR-TSN (Security-and-Safetyaware Scheduling and Routing for TSN) component. We will also present the web-based Graphical User Interface (GUI) of TSNConf, which was built using open source components and will be shared with the community

@misc{Reusch:2020aa,
  author = {Niklas Reusch and Paul Pop},
  title = {TSNConf: Tool Suite for the configuration of Time-Sensitive Networking for Safety- and Security-Critical Applications},
  year = {2020}
}

This article focuses on mixed-criticality applications with functions that have different timing requirements, i.e., hard real-time (HRT), soft real-time (SRT), and functions that are not time-critical (NC). The applications are implemented on distributed cyber-physical systems that use IEEE Time-sensitive Networking (TSN). TSN is the product of an IEEE effort to bring deterministic real-time capabilities to IEEE 802.3 Ethernet. TSN supports the convergence of multiple traffic types, i.e., critical, real-time, and regular “best-effort” traffic within a single network: Time-triggered (TT), where the messages are transmitted based on static schedule tables, Audio-video Bridging (AVB), for dynamically scheduled messages with a guaranteed bandwidth and bounded delays, and Best Effort (BE), for which no timing guarantees are provided. The HRT messages have deadlines, whereas we capture the quality-of-service for the SRT messages using “utility functions.” Given the network topology, the set of application messages, including their routing, and the set of available AVB classes, we are interested in determining the traffic type of each message, such that all the HRT messages are schedulable and the total utility for the SRT messages is maximized. We propose a Tabu Search-based metaheuristic to solve this optimization problem. The proposed proof-of-concept tool has been evaluated using several benchmarks, including two realistic test cases.

@article{Gavrilut:2020aa,
  author = {Voica Gavrilu{\c t} and Paul Pop},
  title = {Traffic-type assignment for TSN-based mixed-criticality cyber-physical systems},
  journal = {ACM Transactions on Cyber-Physical Systems},
  publisher = {Association for Computing Machinery},
  year = {2020},
  doi = {10.1145/3371708}
}

Fog computing has been identified as an enabler for many modern technologies like connected vehicles and the Industrial Internet of Things (IIoT). Such technologies are characterized by the integration of applications with different levels of criticality on shared platforms, which are referred to as mixed-criticality systems. Mixed-criticality systems typically use static scheduling for critical tasks; however, static scheduling is not suitable for scenarios where fog nodes run dynamic noncritical applications that implement, e.g., maintenance checks and data analytics. To address this challenge, in this paper, we differentiate between critical tasks that are statically allocated (called “native”) and dynamic non-critical tasks that may migrate across fog nodes (called “temporary”). We propose a static scheduling approach that maximizes the number of temporary tasks that can be added at runtime, without negatively impacting the already scheduled native tasks. This approach enables fog nodes to become more suitable for IIoT environments by configuring them with extensible schedules for the native tasks. To evaluate our approach, we perform experiments considering several test cases, which show that given a number of native tasks, the generated extensible schedules enable the fog nodes to run a larger number of temporary tasks at the same time. Furthermore, the extensible schedules exhibit 7.8 % less missed deadlines (on averaae), compared to the non-extensible schedules. To address this challenge, in this paper, we differentiate between critical tasks that are statically allocated (called “native”) and dynamic non-critical tasks that may migrate across fog nodes (called “temporary”). We propose a static scheduling approach that maximizes the number of temporary tasks that can be added at runtime, without negatively impacting the already scheduled native tasks. This approach enables fog nodes to become more suitable for IIoT environments by configuring them with extensible schedules for the native tasks. To evaluate our approach, we perform experiments considering several test cases, which show that given a number of native tasks, the generated extensible schedules enable the fog nodes to run a larger number of temporary tasks at the same time. Furthermore, the extensible schedules exhibit 7.8 % less missed deadlines (on averaae), compared to the non-extensible schedules.

@inproceedings{Barzegaran:2020ad,
  author = {Mohammadreza Barzegaran and Vasileios Karagiannis and Avasalcai, {Cosmin Florin} and Paul Pop and Stefan Schulte and Schahram Dustdar},
  title = {Towards Extensibility-Aware Scheduling of Industrial Applications on Fog Nodes},
  booktitle = {Proceedings of 2020 IEEE International Conference on Edge Computing},
  publisher = {IEEE},
  year = {2020},
  doi = {10.1109/EDGE50951.2020.00018},
  url = {https://ieeexplore.ieee.org/xpl/conhome/9136835/proceeding}
}

In this paper we are interested in real-time control applications that are implemented using Fog Computing Platforms consisting of interconnected heterogeneous Fog Nodes (FNs). Similar to previous research and ongoing standardization efforts, we assume that the communication between FNs is achieved via IEEE 802.1 Time Sensitive Networking (TSN). We model the control applications as a set of real-time streams, and we assume that the messages are transmitted using time-sensitive traffic that is scheduled using the Gate Control Lists (GCLs) in TSN. Given a network topology and a set of control applications, we are interested to synthesize the GCLs for messages such that the quality-of-control of applications is maximized and the deadlines of real-time messages are satisfied. We have proposed a Constraint Programming-based solution to this problem, and evaluated it on several test cases.

@inproceedings{Barzegaran:2020ac,
  author = {Mohammadreza Barzegaran and Bahram Zarrin and Paul Pop},
  title = {Quality-of-control-aware scheduling of communication in TSN-based fog computing platforms using constraint programming},
  booktitle = {2nd Workshop on Fog Computing and the IoT},
  publisher = {Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany},
  year = {2020},
  doi = {10.4230/oasics.fog-iot.2020.3}
}

In this paper, we address mixed-criticality applications characterized by their safety criticality and time-dependent performance, which are virtualized on a Fog Computing Platform (FCP). The FCP is implemented as a set of interconnected multicore computing nodes, and brings computation and communication closer to the edge of the network, where the machines are located in industrial applications. We use partitioning and static-cyclic scheduling to provide isolation among mixed-criticality tasks and to guarantee their timing requirements. The temporal and spatial isolation is enforced via partitions, which execute tasks with the same criticality level. We consider that the tasks are scheduled using static cyclic scheduling. We are interested in determining the mapping of tasks to the cores of the fog nodes, the assignment of tasks to the partitions, the partition schedule tables, and the tasks’ schedule tables, such that the Quality-ofControl for the control tasks is maximized and we meet the timing requirements for all tasks, including tasks with lower-criticality levels. We are also interested in determining the periods for control tasks to balance the schedulability and the control performance. We have proposed a Simulated Annealing metaheuristic, which relies on a heuristic algorithm for determining the schedules and partitions, to solve this optimization problem. Our optimization strategy has been evaluated on several test cases, showing the effectiveness of the proposed method.

@article{Barzegaran:2020ab,
  author = {Mohammadreza Barzegaran and Anton Cervin and Paul Pop},
  title = {Performance Optimization of Control Applications on Fog Computing Platforms Using Scheduling and Isolation},
  journal = {IEEE Access},
  publisher = {Institute of Electrical and Electronics Engineers},
  year = {2020},
  doi = {10.1109/ACCESS.2020.2999322}
}

Modern Advanced Driver-Assistance Systems (ADAS) merge critical and non-critical software functions with complex timing requirements and inter-dependencies onto the same integrated hardware platform. Real-time safety-critical automotive applications feature complex dependency chains between tasks (e.g., performing sensing, processing and actuation) which have to satisfy worst-case end-to-end latency constraints. The resulting scheduling problem requires both the assignment of tasks to the available cores of the platform and the computation static schedule tables for the real-time tasks, such that task deadlines, as well as end-to-end task chain constraints, are satisfied. We propose a heuristic approach based on Simulated Annealing (SA) which creates static schedule tables by simulating Earliest Deadline First (EDF) scheduling parameterized by task offsets and local deadlines decided by SA. We evaluate the proposed solution with real-world and synthetic test cases scaled to fit the future requirements of ADAS systems.

@inproceedings{McLean:2020aa,
  author = {McLean, {Shane Daniel Geisler} and Craciunas, {Silviu S.} and {Alexander Juul Hansen}, Emil and Paul Pop},
  title = {Mapping and Scheduling Automotive Applications on ADAS Platforms using Metaheuristics},
  booktitle = {Proceedings of 25th IEEE International Conference on Emerging Technologies and Factory Automation},
  publisher = {IEEE},
  year = {2020},
  doi = {10.1109/ETFA46521.2020.9212029},
  url = {http://www.ieee-etfa.org/2020/}
}

Electric drives are used to control electric motors, which are pervasive in industrial applications. In this paper we propose enhancing the electric drives to fulfil the role of fog nodes within a Fog Computing Platform (FCP). Fog Computing is envisioned as a realization of future distributed architectures in Industry 4.0. We identify the system-level requirements of such an FCP, including requirements that are extracted from the current architecture of drives, which we consider as a baseline. These requirements are then used to design a system-level architecture, which we model using the Architecture Analysis Design Language (AADL). We identify the "technology bricks"(components such as hardware, software, middleware, services, methods and tools) needed to implement the FCP. The proposed fog-based architecture is then used to implement a Conveyor Belt industrial use case. We evaluate the resulting use case on several aspects, demonstrating the usefulness of the proposed fog-based approach. By developing the electric drives as fog nodes, that we call fogification, new offerings like programmability, analytics and connectivity to customer Clouds are expected to increase the added value. Increased flexibility allows drives to assume a larger role in industrial and domestic control systems, instrumenting thus also legacy systems by using drives as the data source.

@inproceedings{Barzegaran:2020aa,
  author = {Mohammadreza Barzegaran and Nitin Desai and Jia Qian and Koen Tange and Bahram Zarrin and Paul Pop and Juha Kuusela},
  title = {Fogification of electric drives: An industrial use case},
  booktitle = {Proceedings of 2020 25th IEEE International Conference on Emerging Technologies and Factory Automation},
  publisher = {IEEE},
  year = {2020},
  doi = {10.1109/ETFA46521.2020.9212010},
  url = {http://www.ieee-etfa.org/2020/}
}

Demanding IoT application requirements such as high dependability and low latency, cannot be satisfied by centralized cloud computing when deploying these applications. Edge computing is emerging as an alternative to deploy demanding IoT applications closer to the edge of the network. However, with edge computing, available resources are distributed among different resource-constrained devices, which cannot host large monolithic applications. We propose a new hierarchical IoT application model, suitable for the distributed nature of edge computing. Thus, a task in the application is modeled using multiple configurations of smaller tasks, each with their own functionality level and resource requirements. For deployment we use a decentralized resource technical framework that finds a satisfiable task mapping on edge devices. Its functionality is inspired by an auction house, having the objectives of (i) deploying an application such that its requirements are met and (ii) empowers edge devices to be in control of their available resources. For the latter, we propose a new decision policy to help edge devices take better decisions regarding the use of local available resource. Our solution enables efficient device resource utilization when deploying IoT applications at the edge.

@inproceedings{Avasalcai:2020aa,
  author = {Cosmin Avasalcai and Bahram Zarrin and Paul Pop and Schahram Dustdar},
  title = {Efficient Hosting of Robust IoT Applications on Edge Computing Platform},
  booktitle = {Proceedings of 4th IEEE International Conference on Fog and Edge Computing},
  publisher = {IEEE},
  year = {2020},
  doi = {10.1109/ICFEC50348.2020.00008},
  url = {https://ieeexplore.ieee.org/xpl/conhome/9136835/proceeding}
}

Cooperative vehicular cyber physical systems (vCPSs) can shape a group of mobile robots that can accomplish a cooperative task using wireless communications and distributed control. To this end, such a cooperative task can be coordinated and managed by a distributed control plane that will be able to encapsulate the required functionality in a layered architecture providing the required interoperability. In this paper, we propose a distributed control plane that consists of the cooperative awareness layer, the communication layer and the distributed control layer. We deal with the distributed control for vCPS employing distributed model predictive control for leader-follower formation control. Next, the design of ultra reliable and low latency wireless communications is specified, where a distributed solution is devised to provide ultra reliable distributed control for cooperative vCPS. Simulation results are obtained in order to highlight the impact of reliability constraint to join/leave manoeuvre for the considered use case.

@inproceedings{Foukalas:2019ac,
  author = {Fotis Foukalas and Paul Pop},
  title = {Ultra reliable distributed control for cooperative vehicular cyber physical systems},
  booktitle = {Proceedings of 13th Annual IEEE International Systems Conference},
  publisher = {IEEE},
  year = {2019},
  doi = {10.1109/SYSCON.2019.8836922},
  url = {https://ieeexplore.ieee.org/xpl/conhome/8826628/proceeding}
}

In this paper we address Industrial IoT control applications which are safety-critical and real-time, and which have very low latency and jitter requirements. These control applications are virtualized as software tasks running on a Fog Computing Platform that brings computing and deterministic communication closer to the edge of the network, where the industrial "things" are located. Due to the demanding dependability and timing requirements, we consider that the tasks are scheduled with a static-cyclic scheduling policy. We are interested to determine the mapping of the tasks and a schedule table of their activation, such that we maximize the quality-of-control for the control tasks and meet the timing requirements for all tasks, including non-critical real-time tasks. We have proposed a Simulated Annealing-based metaheuristic to solve this problem, and we have evaluated the solution on several test cases.

@inproceedings{Barzegaran:2019aa,
  author = {Mohammadreza Barzegaran and Anton Cervin and Paul Pop},
  title = {Towards quality-of-control-aware scheduling of industrial applications on fog computing platforms},
  booktitle = {Proceedings of the 2019 Workshop on Fog Computing and the IoT},
  publisher = {Association for Computing Machinery},
  year = {2019},
  doi = {10.1145/3313150.3313217}
}

@techreport{McLean:2019aa,
  author = {Shane D. McLean and Paul Pop and Silviu S. Craciunas},
  title = {Mapping and scheduling of real-time tasks on multi-core autonomous driving platforms},
  year = {2019}
}

Cooperative vehicular cyber physical systems build a group of entities that can accomplish a cooperative task using the distributed control approaches. To this end, such a cooperative task can be coordinated and managed by a distributed control plane that will be able to encapsulate all the required functionality in a layered architecture providing the required interoperability. Here, the authors propose such a distributed control plane that consists of the cooperative awareness layer, the communication layer and the distributed control layer. Wireless communications play an important role for the mobility provision, taking into account different constraints in order to provide high reliability and low latency. A simulation environment is considered with a leader–follower control format, where the reliability is evaluated. Further, a distributed safety monitoring approach is devised, given a control diagram and mapping of the events to the different components. The event monitoring relies on the self-triggered approach, where a use case is evaluated to highlight the impact of the input and output delays to the model predictive control component of the overall distributed control diagram including the calculation of the number of triggered events.

@article{Foukalas:2019ab,
  author = {Fotis Foukalas and Paul Pop},
  title = {Distributed control plane for safe cooperative vehicular cyber physical systems},
  journal = {IET Cyber-Physical Systems: Theory and Applications},
  publisher = {John Wiley \& Sons Inc.},
  year = {2019},
  doi = {10.1049/iet-cps.2019.0034}
}

To enable mVLSI biochips for point-of-care applications, recent work has focused on reducing the number of off-chip pressure sources, using on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Since these on-chip pneumatic control logic circuits in turn control the fluidic operations, it is very important that they are fault-free, in order to avoid the failure of biochemical applications. For the first time, this paper proposes a design-fortestability (DFT) scheme to test for faults inside on-chip pneumatic control logic circuits, by adding observation pneumatic latches into the circuit.

@article{Potluri:2019aa,
  author = {Seetal Potluri and Paul Pop and Jan Madsen},
  title = {Design-For-Testability of On-Chip Control in mVLSI Biochips},
  journal = {IEEE Design and Test},
  publisher = {IEEE},
  year = {2019},
  doi = {10.1109/MDAT.2018.2873448}
}

Industrial Internet of Things (IIoT) networks are considered the large-scale deployment of IoT devices for industrial applications such as smart manufacturing, harvesting and supply chain management. The Internet of Things (IoT) devices are typically connected over a wireless medium, given the large geographical distribution area and the increasing demand for flexible installations. In some cases, a combination of wired and wireless connectivity can be assumed as common practice. In both scenarios, wireless communications for IIoT networks is a fundamental component of the system architecture that needs to satisfy stringent requirements such as reliable connectivity and minimal delays. Therefore, the dependability of wireless communications for IIoT networks should be carefully studied to provide new solutions, which can guarantee that applications can meet their real-time and reliability requirements while optimizing the control capability of the overall network. This paper focuses on the dependable wireless communications in the IIoT networks, where wireless control and monitoring tasks need to meet stringent real-time and reliability constraints. After reviewing recent solutions and discussing their suitability for IIoT networks, we highlight the yet open challenges that needs to be tackled by both academia and industry.

@inproceedings{Foukalas:2019aa,
  author = {Fotis Foukalas and Paul Pop and Fabrice Theoleyre and Boano, {Carlo Alberto} and Chiara Buratti},
  title = {Dependable Wireless Industrial IoT Networks: Recent Advances and Open Challenges},
  booktitle = {Proceedings of 2019 IEEE European Test Symposium},
  publisher = {IEEE},
  year = {2019},
  doi = {10.1109/ETS.2019.8791551}
}

In this paper, a cooperative solution for vehicle-to-everything (V2X) communications is proposed and presented, which can guarantee reliability and latency requirements for 5G enhanced V2X (eV2X) services. Cooperation is useful for both in-coverage and out-of-coverage vehicular communications scenarios. The proposed solution relies on the sidelink (SL) device-to-device (D2D) communications for V2X communications. In this work, we first provide a performance evaluation of SL D2D V2X communications in terms of resource allocation and scheduling. The resource allocation is known as mode 3 and 4 SL D2D communications and the scheduling is using a semi-persistent scheduling (SPS) approach. Simulation results are obtained in order to identify and highlight the reliability trade-offs considering different payload sizes and SPS parameters. In the sequel, a cooperative solution that decreases transmission collision probability is devised and presented, which is able to significantly improve the reliability of future 5G enhanced vehicle-to-everything (eV2X) communications. Different application scenarios are simulated to obtain results that can guarantee the latency also requirements per 5G eV2X use case as specified in 3GPP Rel.16 towards ultra reliable and low latency communications (URLLC).

@article{Bonjorn:2019aa,
  author = {Nestor Bonjorn and Fotios Foukalas and {Canellas Cruz}, Ferran and Paul Pop},
  title = {Cooperative Resource Allocation and Scheduling for 5G eV2X Services},
  journal = {IEEE Access},
  publisher = {Institute of Electrical and Electronics Engineers},
  year = {2019},
  doi = {10.1109/ACCESS.2018.2889190}
}

Distributed safety-critical applications in industrial automation, aerospace, and automotive, require worst-case end-to-end latency analysis for critical communication flows in order to prove their correct behavior in the temporal domain.With the advent of Time Sensitive Networks (TSN), distributed applications can be built on top of standard Ethernet technologies without sacrificing real-time characteristics. The time-based transmission selection and clock synchronization mechanism defined in TSN enable the real-time transmission of frames based on a global schedule configured through so-called Gate Control Lists (GCLs). This paper has an enhancement of allowing a mixture of the priority-based scheduling and time-triggered, which expand the solution space for GCLs. Then, it is necessary to analyze the latency bounds for the critical traffic in the TSN network. In this work, we start from the assumption that the GCLs, i.e. the communication schedules, and the traffic class (priority) assignment for critical flows are given for each output port and derive, using network calculus, an analysis of the worst-case delays that individual critical flows can experience along the hops from sender to receiver(s). Our method can be employed for the analysis of TSN networks where the GCLs have been created in advance, as well as for driving the GCL synthesis that explores a larger solution space than previous methods, which required a complete isolation of transmission events from different traffic classes. We validate our model and analysis by performing experiments on both synthetic and real-world use-cases, showing the scalability of our implementation as well as the impact of certain GCL properties (gate overlapping and traffic class assignments) on the worst-case latency of critical communication flows.

@article{Zhao:2018aa,
  author = {Luxi Zhao and Paul Pop and Craciunas, {Silviu S.}},
  title = {Worst-case Latency Analysis for IEEE 802.1Qbv Time Sensitive Networks using Network Calculus},
  journal = {IEEE Access},
  publisher = {Institute of Electrical and Electronics Engineers},
  year = {2018},
  doi = {10.1109/ACCESS.2018.2858767}
}

IEEE 802.1 Time-Sensitive Networking (TSN) is a set of IEEE standards that extend Ethernet for safety-critical and real-time applications. TSN is envisioned to be widely used in several applications areas, from industrial automation to in-vehicle networking. TSN supports mixed-criticality applications via multiple traffic classes: Time-Triggered (TT) communication, Audio-Video-Bridging (AVB) streams with bounded end-to-end latency as well as Best-Effort messages. TT traffic is scheduled via Gate Control Lists (GCLs) specified for each queue of an egress port. Although researchers have started to propose approaches for the GCL synthesis, all the work so far has ignored lower priority real-time traffic such as AVB, resulting in GCLs that increase the worst-case delays of AVB traffic rendering it unschedulable. In this paper, we propose a GCL synthesis approach based on a Greedy Randomized Adaptive Search Procedure, which takes into account the AVB traffic, such that both TT and the AVB traffic are schedulable. Our approach is evaluated on several test cases.

@inproceedings{Gavrilut:2018ab,
  author = {Voica Gavrilut and Paul Pop},
  title = {Scheduling in time sensitive networks (TSN) for mixed-criticality industrial applications},
  booktitle = {Proceedings of 2018 14th IEEE International Workshop on Factory Communication Systems},
  publisher = {IEEE},
  year = {2018},
  doi = {10.1109/WFCS.2018.8402374},
  url = {https://ieeexplore.ieee.org/xpl/conhome/8396320/proceeding}
}

A microfluidic valve and a microfluidic inverter comprising the valve is disclosed. The microfluidic valve comprising a first rigid layer having a first side; a second rigid layer having a second side facing the first side of the first rigid layer; a flexible layer being arranged between the first side of the first rigid layer and the second side of the second rigid layer, in a first state the flexible layer prevents fluid connection between a first input channel and a first output channel, in a second state the flexible layer protrudes into a first indentation providing fluid connection between the first input channel and the first output channel; and a first control gate channel configured to receive a first fluidic control pressure.

@misc{Potluri:2018aa,
  author = {Seetal Potluri and Paul Pop and Jan Madsen and Schneider, {Alexander R{\"u}diger}},
  title = {Microfluidic valve},
  year = {2018}
}

@techreport{Luxi-Zhao:2018aa,
  author = {Luxi Zhao, Paul Pop, Zhong Zheng, Hugo Daigmorte and Marc Boyer},
  title = {Improving Worst-Case End-to-End Delay Analysis of Multiple Classes of AVB Traffic in TSN Networks using Network Calculus},
  year = {2018}
}

In this paper, we present advances of sidelink (SL) device-to-device (D2D) communications as a key-enabling technology for 5G enhanced vehicular-to-everything (eV2X) communications. We provide an overview about the resource allocation and scheduling of different SL D2D modes under in-coverage and out-of-coverage application scenarios. Moreover, we present the scheduling for SL D2D V2X communications, which relies on semi-persistent scheduling (SPS) as proposed within the 3GPP specification. Simulations were carried out to evaluate the performance in terms of collision probability assuming different values of the key parameters such as resource reselection interval (RRI) and resource selection window. We finally discuss about the open technical challenges for ultra-reliable and low-latency communications as distilled from the 5G V2X use cases introduced in 3GPP Rel.15. A cooperative resource allocation and scheduling solution is also given, where a more detailed version is considered our future work on this topic.

@inproceedings{Bonjorn:2018aa,
  author = {Nestor Bonjorn and Fotis Foukalas and Paul Pop},
  title = {Enhanced 5G V2X services using sidelink device-to-device communications},
  booktitle = {Proceedings of 17th Annual Mediterranean Ad Hoc Networking Workshop},
  publisher = {IEEE},
  year = {2018},
  doi = {10.23919/MedHocNet.2018.8407085},
  url = {http://medhocnet18.cnit.it/}
}

In this article, we advocate for the use of IEEE 802.1 Time-Sensitive Networking (TSN) as deterministic transport for the network layer of fog computing in industrial automation. We give an overview of the relevant TSN protocol services and motivate the use of TSN. We propose a configuration agent architecture based on IEEE 802.1Qcc and OPC Unified Architecture (OPC UA), capable of performing runtime network configuration. We briefly present the configuration challenges for scheduled networks (considering a subset of TSN mechanisms), and illustrate one problem: the configuration of schedule tables of such networks for hard real-time control applications. We propose a list scheduling-based heuristic to solve this problem. Our evaluation and comparison to previous work demonstrate the feasibility of reconfiguring the scheduled network at runtime for industrial applications within the fog.

@article{Pop:2018aa,
  author = {Paul Pop and Raagaard, {Michael Lander} and Marina Gutierrez and Wilfried Steiner},
  title = {Enabling Fog Computing for Industrial Automation Through Time-Sensitive Networking (TSN)},
  journal = {IEEE Communications Standards Magazine},
  publisher = {Institute of Electrical and Electronics Engineers Inc.},
  year = {2018},
  doi = {10.1109/MCOMSTD.2018.1700057}
}

IEEE 802.1 Time-Sensitive Networking (TSN) is a set of amendments to the IEEE 802.1 standard that enable safety-critical and real-time behavior over Ethernet for the industrial automation and automotive domains. Selected TSN mechanisms offer the possibility to emulate the well-known traffic classes found in mixed-criticality distributed systems: Time-Triggered (TT) communication with low jitter and bounded end-to-end latency, Audio-Video-Bridging (AVB) streams with bounded end-to-end latency, as well as general Best-Effort messages, which have no timing guarantees. Critical traffic is guaranteed via the global network schedule which is stored in so-called Gate Control Lists (GCLs) and controls the timely behavior of frames for each queue of an egress port. Although researchers have started to propose approaches for the routing and scheduling (i.e., GCL synthesis) of TT traffic, all previous research has ignored lower priority real-time traffic such as AVB, resulting in TT configurations that may increase the worst-case delays of AVB traffic, rendering it unschedulable. In this paper, we propose a joint routing and scheduling approach for TT traffic, which takes into account the AVB traffic, such that both TT and the AVB traffic are schedulable. We extensively evaluate our approach on a number of synthetic as well as realistic test cases.

@article{Gavrilut:2018aa,
  author = {Voica Gavrilut and Luxi Zhao and Raagaard, {Michael L.} and Paul Pop},
  title = {AVB-Aware Routing and Scheduling of Time-Triggered Traffic for TSN},
  journal = {IEEE Access},
  publisher = {Institute of Electrical and Electronics Engineers},
  year = {2018},
  doi = {10.1109/ACCESS.2018.2883644}
}

Microfluidic biochips are replacing the conventional biochemical analysers integrating the necessary functions on- chip. We are interested in Flow-Based Microfluidic Biochips, where a continuous flow of liquid is manipulated using integrated microvalves. Using microvalves and channels, more complex Fluidic Units (FUs) such as switches, micropumps, mixers and separators can be constructed. To support the reliable and efficient functionality of these FUs, we propose a novel component that assures accurate fluid volume metering and transport. Using vents, trapped air is expelled from the chip, which allows to align fluid to a precise location and accurately meter its volume. Furthermore can this component be used to detect erroneous (insufficient) fluid volumes. We have fabricated several prototypes to demonstrate and evaluate the functionality of our proposed component.

@inproceedings{Schneider:2018aa,
  author = {Alexander Schneider and Paul Pop and Jan Madsen},
  title = {A novel metering component for volume management in flow-based microfluidic biochips},
  booktitle = {Proceedings of 20th Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS},
  publisher = {IEEE},
  year = {2018},
  doi = {10.1109/DTIP.2018.8394191}
}

Microfluidic biochips are replacing the conventional biochemical analysers integrating the necessary functions onchip. We are interested in Flow-Based Microfluidic Biochips (FBMB), where a continuous flow of liquid is manipulated using integrated microvalves. Using microvalves and channels, more complex Fluidic Units (FUs) such as switches, micropumps, mixers and separators can be constructed. When running a biochemical application on a FBMB, fluid volumes are dispensed from input reservoirs and used by the FUs. Given a biochemical application and a biochip, we are interested in determining the fluid volume assignment for each operation of the application, such that the FUs volume requirements are satisfied, while over- and underflow are avoided and the total volume of fluid used is minimized. We propose an algorithm for this fluid assignment problem. Compared to previous work, our method is able to minimize the fluid consumption through optimal fluid assignment and reuse of fluid waste. Due to the algorithm's low complexity, fluid requirements can also be calculated during runtime for error recovery or statically unknown cases.

@inproceedings{Schneider:2017ac,
  author = {Schneider, {Alexander R{\"u}diger} and Paul Pop and Jan Madsen},
  title = {Waste-aware fluid volume assignment for flow-based microfluidic biochips},
  booktitle = {2017 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)},
  publisher = {IEEE},
  year = {2017},
  doi = {10.1109/DTIP.2017.7984507}
}

Recent advancements in microfluidic biochips allow for easier and faster design and fabrication of increasingly complex biochips to replace conventional laboratories. A roadblock in the deployment of biochips however is their low reliability. Physical defects can be introduced during the fabrication process, and may lead to failure of the biochemical application. This can be costly because of the reduced manufacturing yield, the need to redo lengthy experiments, using expensive reagents, and can be safety-critical, e.g., in case of a cancer misdiagnosis. Researchers have started to propose fault models and test techniques for continuous flow biochips. Six typical defects: Block, leak, misalignment, faulty pumps, degradation of valves and dimensional errors have been identified. The resulting faults can be abstracted into blocks and leaks for simplicity. Both fault types can occur in the control-as well as the flow channel, some common causes being environmental particles, imperfections in molds or bubbles in the PDMS gel. While some faults may be detected before the execution of an application by introducing a test run, other faults occur only during runtime as a result of deterioration or caused by the applied pressure. If such a fault is detected during runtime, e.g. with a CCD camera, we propose a just in time solution that calculates and assigns fluid volumes to alternate components and routes allowing for the completion of the application despite the occurring fault.

@inbook{Schneider:2017ab,
  author = {Schneider, {Alexander R{\"u}diger} and Paul Pop and Jan Madsen},
  title = {Volume management for fault-tolerant continuous-flow microfluidics},
  booktitle = {Proceedings of 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems},
  publisher = {IEEE},
  year = {2017},
  doi = {10.1109/DFT.2017.8244447},
  url = {https://ieeexplore.ieee.org/xpl/conhome/8227263/proceeding}
}

Flow-based microfluidic biochips have attracted much attention in the EDA community due to their miniaturized size and execution efficiency. Previous research, however, still follows the traditional computing model with a dedicated storage unit, which actually becomes a bottleneck of the performance of biochips. In this paper, we propose the first architectural synthesis framework considering distributed storage constructed temporarily from transportation channels to cache fluid samples. Since distributed storage can be accessed more efficiently than a dedicated storage unit and channels can switch between the roles of transportation and storage easily, biochips with this distributed computing architecture can achieve a higher execution efficiency even with fewer resources. Experimental results confirm that the execution efficiency of a bioassay can be improved by up to 28% while the number of valves in the biochip can be reduced effectively.

@inproceedings{Liu:2017aa,
  author = {Chunfeng Liu and Bing Li and Hailong Yao and Paul Pop and Tsung-Yi Ho and Ulf Schlichtmann},
  title = {Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage},
  booktitle = {Proceedings of the 54th ACM/EDAC/IEEE Design Automation Conference (DAC)},
  publisher = {IEEE},
  year = {2017},
  doi = {10.1145/3061639.3062334}
}

The automotive electronic architectures have moved from federated architectures, where one function is implemented in one ECU (Electronic Control Unit), to distributed architectures, consisting of several multicore ECUs. In addition, multicore ECUs are being adopted because of better performance, cost, size, fault-tolerance and power consumption. Automotive manufacturers use AUTomotive Open System ARchitecture (AUTOSAR) as the standardized software architecture for ECUs. With AUTOSAR, the functionality is modeled as a set of software components composed of subtasks, called runnables. In this paper we propose an approach for the automatic software functionality assignment to multicore distributed architectures, implemented as a software tool. The AUTOMAP, decides: the (i) mapping of software components to multicore ECUs, (ii) the assignment of runnables to the ECU cores, (iii) the clustering of runnables into tasks and (iv) the mapping of tasks to “OS-Applications”, such that timing and mapping constraints are satisfied. AUTOMAP has been developed to handle large industrialsized use cases, fine-grained realistic mapping and timing constraints, and to produce outputs that support the system engineer in the mapping task. We have successfully evaluated AUTOMAP on several realistic use cases from Volvo Trucks.

@inproceedings{Avasalcai:2017ab,
  author = {Avasalcai, {Cosmin Florin} and Dhanesh Budhrani and Paul Pop},
  title = {Towards industry strength mapping of AUTOSAR automotive functionality on multicore architectures: work in progress},
  booktitle = {CASES '17 Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion},
  publisher = {Association for Computing Machinery},
  year = {2017},
  doi = {10.1145/3125501.3125623}
}

TTEthernet is a deterministic, synchronized and congestion-free network protocol based on the Ethernet standard and compliant with the ARINC 664p7 standard network. It supports safety-critical real-time applications by offering different traffic classes: static time-triggered (TT) traffic, rate-constrained (RC) traffic with bounded end-to-end latencies and best-effort traffic, for which no guarantees are provided. TTEthernet uses three integration policies for sharing the network among the traffic classes: shuffling, preemption and timely block. In this paper, we propose an analysis based on network calculus (NC) to determine the worst-case end-to-end delays of RC traffic in TTEthernet. The main contribution of this paper is capturing the effects of all the integration policies on the latency bounds of RC traffic using NC, and the consideration of relative frame offsets of TT traffic to reduce the pessimism of the RC analysis. The proposed analysis is evaluated on several test cases, including realistic applications (e.g., Orion Crew Exploration Vehicle), and compared to related works.

@article{Zhao:2017ab,
  author = {Luxi Zhao and Paul Pop and Qiao Li and Junyan Chen and Huagang Xiong},
  title = {Timing analysis of rate-constrained traffic in TTEthernet using network calculus},
  journal = {Real-Time Systems},
  publisher = {Springer New York LLC},
  year = {2017},
  doi = {10.1007/s11241-016-9265-0},
  url = {http://dx.doi.org/10.1007/s11241-016-9265-0}
}

Time-Sensitive Networking (TSN) is a collection of standards that extend Ethernet to support safety-critical and real-time applications. TSN integrates multiple traffic types, i.e., Time-Triggered (TT) traffic scheduled based on Gate-Control-Lists (GCLs), Audio-Video-Bridging (AVB) traffic that requires bounded latencies, and Best-Effort (BE) traffic, for which no guarantees are provided. This paper proposes a Network Calculus-based approach to determine the worst-case end-to-end delays of AVB traffic in a TSN network with both non-preemption and preemption modes. We consider the effects of TT traffic due to GCLs, "guard bands", i.e., time windows that block other traffic from transmitting, and preemption overhead on the service for AVB traffic. We provide a proof of non-overflow condition for AVB credit, which is used to control the AVB traffic transmission. The analysis method is evaluated on realistic test cases, and compared to related work.

@techreport{Zhao:2017aa,
  author = {Luxi Zhao and Paul Pop and Zhong Zheng and Qiao Li},
  title = {Timing Analysis of AVB Traffic in TSN Networks using Network Calculus},
  booktitle = {Proceedings of 2018 IEEE Real-Time and Embedded Technology and Applications Symposium},
  publisher = {IEEE},
  year = {2017},
  doi = {10.1109/RTAS.2018.00009},
  url = {https://ieeexplore.ieee.org/xpl/conhome/8429504/proceeding}
}

Microfluidic VLSI (mVLSI) biochips help perform biochemistry at miniaturized scales, thus enabling cost, performance and other benefits. Although biochips are expected to replace biochemical labs, including point-of-care devices, the off-chip pressure actuators and pumps are bulky, thereby limiting them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip physical design was performed assuming that all of the control logic is off-chip. However, the problem of mVLSI biochip physical design changes significantly, with introduction of on-chip control, since along with physical synthesis, we also need to (i) perform on/off-chip control partitioning, (ii) on-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully applied to generate biochip layouts with integrated on-chip pneumatic control.

@inproceedings{Potluri:2017aa,
  author = {Seetal Potluri and Schneider, {Alexander R{\"u}diger} and Martin H{\o}rslev-Petersen and Paul Pop and Jan Madsen},
  title = {Synthesis of on-chip control circuits for mVLSI biochips},
  booktitle = {Proceedings of 20th Design, Automation and Test in Europe},
  publisher = {IEEE},
  year = {2017},
  doi = {10.23919/DATE.2017.7927284}
}

@misc{Avasalcai:2017aa,
  author = {Cosmin Avasalcai and Paul Pop},
  title = {ShipNet},
  year = {2017}
}

Microfluidic laboratories-on-chip (LoCs) are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis onchip. There are several types of LoCs, each having its advantages and limitations. In this paper we are interested in flow-based LoCs, in which a continuous flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers and multiplexers, can be built. We consider that the architecture of the LoC is given, and we are interested in synthesizing an implementation, consisting of the binding of operations in the application to the functional units of the architecture, the scheduling of operations and the routing and scheduling of the fluid flows, such that the application completion time is minimized. To solve this problem, we propose a List Schedulingbased Application Mapping (LSAM) framework and evaluate it by using real-life as well as synthetic benchmarks. When biochemical applications contain fluids that may adsorb on the substrate on which they are transported, the solution is to use rinsing operations for contamination avoidance. Hence, we also propose a rinsing heuristic, which has been integrated in the LSAM framework.

@article{Minhass:2017aa,
  author = {Minhass, {Wajid Hassan} and Jeffrey McDaniel and Raagaard, {Michael Lander} and Philip Brisk and Paul Pop and Jan Madsen},
  title = {Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip},
  journal = {I E E E Transactions on Computer - Aided Design of Integrated Circuits and Systems},
  publisher = {Institute of Electrical and Electronics Engineers Inc.},
  year = {2017},
  doi = {10.1109/TCAD.2017.2729463}
}

This paper presents an overview of the ECSEL project entitled ―Safe Cooperating Cyber-Physical Systems using Wireless Communication‖ (SafeCOP), which runs during the period 2016–2019. SafeCOP targets safety-related Cooperating Cyber-Physical Systems (CO-CPS) characterised by use of wireless communication, multiple stakeholders, dynamic system definitions (openness), and unpredictable operating environments. SafeCOP will provide an approach to the safety assurance of CO-CPS, enabling thus their certification and development. The project will define a runtime manager architecture for runtime detection of abnormal behaviour, triggering if needed a safe degraded mode. SafeCOP will also develop methods and tools, which will be used to produce safety assurance evidence needed to certify cooperative functions. SafeCOP will extend current wireless technologies to ensure safe and secure cooperation, and also contribute to new standards and regulations, by providing certification authorities and standardization committees with the scientifically validated solutions needed to craft effective standards extended to also address cooperation and system-of-systems issues. The project has 28 partners from 6 European countries, and a budget of about 11 million Euros corresponding to about 1,300 person-months.

@article{Pop:2017aa,
  author = {Paul Pop and Detlef Scholle and Irfan Sljivo and Hans Hansson and Gunnar Widforss and Malin Rosqvist},
  title = {Safe Cooperating Cyber-Physical Systems using Wireless Communication},
  journal = {Microprocessors and Microsystems},
  publisher = {Elsevier},
  year = {2017},
  doi = {10.1016/j.micpro.2017.07.003}
}

Microfluidic biochips are replacing the conventional biochemical analyzers integrating the necessary functions on-chip. We are interested in flow-based biochips, where a continuous flow of liquid is manipulated using integrated microvalves, controlled from external pressure sources via off-chip control pins. Recent research has addressed the physical design of such biochips. However, such research has so far ignored the pin-count, which rises with the increase in the number of microvalves. Given a biochip architecture and a biochemical application, we propose an algorithm for reducing the number of control pins required to run the application. The proposed algorithm has been evaluated on several biochips, including the AquaFlux biochip from Microfluidic Innovations LLC.

@article{Schneider:2017aa,
  author = {Alexander Schneider and Paul Pop and Jan Madsen},
  title = {Pin-count reduction for continuous flow microfluidic biochips},
  journal = {Microsystem Technologies},
  publisher = {Springer Science and Business Media Deutschland GmbH},
  year = {2017},
  doi = {10.1007/s00542-017-3401-1}
}

Routing-based synthesis for digital microfluidic biochips yields faster assay execution times compared to module-based synthesis. We show that routing-based synthesis can lead to deadlocks and livelocks in specific cases, and that dynamically detecting them and adjusting the probabilities associated with different droplet movements can alleviate the situation. We also introduce methods to improve the efficiency of wash droplet routing during routing-based synthesis, and to support non-reconfigurable modules, such as integrated heaters and detectors. We obtain increases in success rates when dealing with resource-constrained chips and reductions in average assay execution time.

@article{Windh:2017aa,
  author = {Skyler Windh and Calvin Phung and Grissom, {Daniel T.} and Paul Pop and Philip Brisk},
  title = {Performance Improvements and Congestion Reduction for Routing-based Synthesis for Digital Microfluidic Biochips},
  journal = {I E E E Transactions on Computer - Aided Design of Integrated Circuits and Systems},
  publisher = {Institute of Electrical and Electronics Engineers},
  year = {2017},
  doi = {10.1109/TCAD.2016.2557726},
  url = {http://dx.doi.org/10.1109/TCAD.2016.2557726}
}

@techreport{Raagaard:2017aa,
  author = {Michael Lander Raagaard and Paul Pop},
  title = {Optimization algorithms for the scheduling of IEEE 802.1 Time-Sensitive Networking (TSN)},
  year = {2017}
}

Time-Sensitive Networking (TSN) is a set of IEEE standards that extend Ethernet for safety-critical and real-time applications. TSN is envisioned to be widely used in several applications areas, from industrial automation to in-vehicle networking. A TSN network is composed of end systems interconnected by physical links and bridges (switches). The data in TSN is exchanged via streams. We address safety-critical real-time systems, and we consider that the streams use the Urgency-Based Scheduler (UBS) traffic-type, suitable for hard real-time traffic. We are interested in determining a fault-tolerant network topology, consisting of redundant physical links and bridges, the routing of each stream in the applications, such that the architecture cost is minimized, the applications are fault-tolerant (i.e., the critical streams have redundant disjoint routes), and the timing constraints of the applications are satisffied. We propose three approaches to solve this optimization problem: (1) a heuristic solution, (2) a Greedy Randomized Adaptive Search Procedure (GRASP) metaheuristic, and (3) a Constraint Programmingbased model. The approaches are evaluated on several test cases, including a test case from General Motors Company

@inproceedings{Gavrilut:2017aa,
  author = {Gavrilut, {Voica Maria} and Bahram Zarrin and Paul Pop and Soheil Samii},
  title = {Fault-Tolerant Topology and Routing Synthesis for IEEE Time-Sensitive Networking},
  booktitle = {Proceedings of the 25th International Conference on Real-Time Networks and Systems},
  publisher = {Association for Computing Machinery},
  year = {2017},
  doi = {10.1145/3139258.3139284},
  url = {http://dx.doi.org/10.1145/3139258.3139284}
}

Microfluidic-based lab-on-a-chips have emerged as a popular technology for implementation of different biochemical test protocols used in medical diagnostics. However, in the manufacturing process or during operation of such chips, some faults may occur that leads to damage of the chip, which in turn results in wastage of expensive reagent fluids. In order to make the chip fault-tolerant, the state-of-the-art technique adopts simulated annealing (SA) based approach to synthesize a fault-tolerant architecture. However, the SA method is time consuming and non-deterministic with over-simplified model that usually derive sub-optimal results. Thus, we propose a progressive optimization procedure for the synthesis of fault-tolerant flow-based microfluidic biochips. Simulation results demonstrate that proposed method is efficient compared to the state-of-the-art techniques and can provide effective solutions in 88% (on average) less CPU time compared to state-of-the-art technique over three benchmark bioprotocols.

@inproceedings{Huang:2017aa,
  author = {Huang, {Wei Lun} and Ankur Gupta and Sudip Roy and Tsung-Yi Ho and Paul Pop},
  title = {Fast architecture-level synthesis of fault-tolerant flow-based microfluidic biochips},
  booktitle = {Proceedings of the 2017 Design, Automation and Test in Europe},
  publisher = {IEEE},
  year = {2017},
  doi = {10.23919/DATE.2017.7927262}
}

In this paper we are interested in mixed-criticality applications, which have functions with different timing requirements, i.e., hard real-time (HRT), soft real-time (SRT) and functions that are not time-critical (NC). The applications are implemented on distributed architectures that use the TTEthernet protocol for communication. TTEthernet supports three traffic classes: Time-Triggered (TT), where frames are transmitted based on static schedule tables; Rate Constrained (RC), for dynamic frames with a guaranteed bandwidth and bounded delays; and Best Effort (BE), for which no timing guarantees are provided. HRT messages have deadlines, whereas for SRT messages we capture the quality-of-service using "utility functions". Given the network topology, the set of application messages and their routing, we are interested to determine the traffic class of each message, such that all HRT messages are schedulable and the total utility for SRT messages is maximized. For the TT frames we decide their schedule tables, and for the RC frames we decide their bandwidth allocation. We propose aTabu Search-based metaheuristic to solve this optimization problem. The proposed approach has been evaluated using several benchmarks, including two realistic test cases.

@article{Gavrilut:2016aa,
  author = {Voica Gavrilut and Paul Pop},
  title = {Traffic Class Assignment for Mixed-Criticality Frames in TTEthernet},
  journal = {SIGBED Review},
  booktitle = {SIGBED Review},
  publisher = {Association for Computing Machinery},
  year = {2016},
  doi = {10.1145/3015037.3015042},
  url = {http://ecrts.eit.uni-kl.de/rtn2016}
}

This paper presents an overview of the ECSEL project entitled "Safe Cooperating Cyber-Physical Systems using Wireless Communication" (SafeCOP), which runs during the period 2016 – 2019. SafeCOP targets safety-related Cooperating Cyber-Physical Systems (CO-CPS) characterised by use of wireless communication, multiple stakeholders, dynamic system definitions (openness), and unpredictable operating environments. SafeCOP will provide an approach to the safety assurance of CO-CPS, enabling thus their certification and development. The project will define a runtime manager architecture for runtime detection of abnormal behaviour, triggering if needed a safe degraded mode. SafeCOP will also develop methods and tools, which will be used to produce safety assurance evidence needed to certify cooperative functions. SafeCOP will extend current wireless technologies to ensure safe and secure cooperation. SafeCOP will also contribute to new standards and regulations, by providing certification authorities and standardization committees with the scientifically validated solutions needed to craft effective standards extended to also address cooperation and system-of-systems issues. The project has 28 partners from 6 European countries, and a budget of about 11 million Euros corresponding to about 1,300 person-months.

@inproceedings{Pop:2016aa,
  author = {Paul Pop and Detlef Scholle and Hans Hansson and Gunnar Widforss and Malin Rosqvist},
  title = {The SafeCOP ECSEL Project: Safe Cooperating Cyber-Physical Systems using Wireless Communication},
  booktitle = {EUROMICRO Digital System Design Conference},
  publisher = {IEEE},
  year = {2016},
  doi = {10.1109/DSD.2016.25}
}

Digital microfluidic biochips (DMBs) are microfluidic devices that manipulate droplets on an array of electrodes. Microfluidic operations, such as transport, mixing, and split, are performed on the electrode array to perform a biochemical application. All previous work assumes that the DMB architecture is given and most approaches consider a rectangular shape for the electrode array. However, nonrectangular application-specific architectures are common in practice. Hence, in this paper, we propose an approach to the synthesis of application-specific architectures, such that the cost of the architecture is minimized and the timing constraints of the biochemical application are satisfied. DMBs can be affected by permanent faults, which may lead to the failure of the biochemical application. Our approach introduces redundant electrodes to synthesize fault-tolerant architectures aiming at increasing the yield of DMBs. We have used a tabu search metaheuristic for this architecture synthesis problem. We have proposed a technique to evaluate the architecture alternatives visited during the search, in terms of their impact on the timing constraints of the application. The proposed architecture synthesis approach has been evaluated using several benchmarks.

@article{Alistar:2016aa,
  author = {Alistar, Mirela and Pop, Paul and Madsen, Jan},
  title = {Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  publisher = {IEEE Press},
  year = {2016},
  doi = {10.1109/TCAD.2016.2528498},
  url = {http://dx.doi.org/10.1109/TCAD.2016.2528498}
}

In this paper we are interested in safety-critical real-time applications implemented on distributed architectures using the Time-Sensitive Networking (TSN) standard. The ongoing standardization of TSN is an IEEE effort to bring deterministic real-time capabilities into the IEEE 802.1 Ethernet standard supporting safety-critical systems and guaranteed Quality-of-Service. TSN will support Time-Triggered (TT) communication based on schedule tables, Audio-Video-Bridging (AVB) streams with bounded end-to-end latency as well as Best-Effort messages. We consider that we know the topology of the network as well as the routes and schedules of the TT streams. We are interested to determine the routing of the AVB streams such that all frames are schedulable and their worst-case end-to-end delay is minimized. We have proposed a search-space reduction technique and a Greedy Randomized Adaptive Search Procedure (GRASP)-based heuristic for this routing optimization problem. The proposed approaches has been evaluated using several test cases.

@article{Sune-Molgaard-Laursen:2016aa,
  author = {Sune M{\o}lgaard Laursen and Paul Pop and Wilfried Steiner},
  title = {Routing Optimization of AVB Streams in TSN Networks},
  journal = {SIGBED Review},
  publisher = {Association for Computing Machinery},
  year = {2016},
  doi = {10.1145/3015037.3015044},
  url = {http://ecrts.eit.uni-kl.de/rtn2016}
}

@article{Windh:2016aa,
  author = {Skyler Windh and Calvin Phung and Daniel Grissom and Paul Pop and Philip Brisk},
  title = {Performance Improvements and Congestion Reduction for Routing-based Synthesis for Digital Microfluidic Biochips},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year = {2016}
}

@book{Pop:2016ab,
  author = {Paul Pop and Wajid Hassan Minhass and Seetal Potluri and Jan Madsen},
  title = {Microfluidic Very Large Scale Integration: Modeling, Simulation, Testing, Compilation and Physical Synthesis},
  publisher = {Springer International Publishing AG},
  year = {2016},
  doi = {10.1007/978-3-319-29599-2}
}

@book{Pop:2015aa,
  author = {Paul Pop and Mirela Alistar and Elena Stuart and Jan Madsen},
  title = {Fault-Tolerant Digital Microfluidic Biochips: Compilation and Synthesis},
  publisher = {Springer International Publishing AG},
  year = {2016},
  doi = {10.1007/978-3-319-23072-6}
}

In this paper we are interested in safety-critical real-time applications implemented on distributed architectures supporting the Time-SensitiveNetworking (TSN) standard. The ongoing standardization of TSN is an IEEE effort to bring deterministic real-time capabilities into the IEEE 802.1 Ethernet standard supporting safety-critical systems and guaranteed Quality-of-Service. TSN will support Time-Triggered (TT) communication based on schedule tables, Audio-Video-Bridging (AVB) flows with bounded end-to-end latency as well as Best-Effort messages. We first present a survey of research related to the optimization of distributed cyber-physical systems using real-time Ethernet for communication. Then, we formulate two novel optimization problems related to the scheduling and routing of TT and AVB traffic in TSN. Thus, we consider that we know the topology of the network as well as the set of TT and AVB flows. We are interested to determine the routing of both TT and AVB flows as well as the scheduling of the TT flows such that all frames are schedulable and the AVB worst-case end-to-end delay is minimized. We have proposed an Integer Linear Programming (ILP) formulation for the scheduling problem and a Greedy Randomized Adaptive Search Procedure (GRASP)-based heuristic for the routing problem. The proposed approaches have been evaluated using several test cases.

@article{Pop:2016ac,
  author = {Paul Pop and {Lander Raagaard}, Michael and Craciunas, {Silviu S.} and Wilfried Steiner},
  title = {Design Optimization of Cyber-Physical Distributed Systems using IEEE Time-sensitive Networks (TSN)},
  journal = {IET Cyber-Physical Systems: Theory and Applications},
  publisher = {Institution of Engineering and Technology (IET)},
  year = {2016},
  doi = {10.1049/iet-cps.2016.0021},
  url = {http://dx.doi.org/10.1049/iet-cps.2016.0021}
}

Abstract In this paper, we are interested in the design of real-time applications with security, safety, timing, and energy requirements. The applications are scheduled with cyclic scheduling, and are mapped on distributed heterogeneous architectures. Cryptographic services are deployed to satisfy security requirements on confidentiality of messages, task replication is used to enhance system reliability, and dynamic voltage and frequency scaling is used for energy efficiency of tasks. It is challenging to address these factors simultaneously, e.g., better security protections need more computing resources and consume more energy, while lower voltages and frequencies may impair schedulability and security, and also lead to reliability degradation. We introduce a vulnerability based method to quantify the security performance of communications on distributed systems. We then focus on determining the appropriate security measures for messages, the voltage and frequency levels for tasks, and the schedule tables such that the security and reliability requirements are satisfied, the application is schedulable, and the energy consumption is minimized. We propose a Tabu Search based metaheuristic to solve this problem. Extensive experiments and a real-life application are conducted to evaluate the proposed techniques.

@article{Jiang:2016aa,
  author = {Wei Jiang and Paul Pop and Ke Jiang},
  title = {Design optimization for security- and safety-critical distributed real-time applications},
  journal = {Microprocessors and Microsystems},
  publisher = {Elsevier},
  year = {2016},
  doi = {http://dx.doi.org/10.1016/j.micpro.2016.08.002},
  url = {http://www.sciencedirect.com/science/article/pii/S0141933116301375}
}

The automotive electronic architectures have moved from federated architectures, where one function is implemented in one ECU (Electronic Control Unit), to distributed architectures, where several functions may share resources on an ECU. In addition, multicore ECUs are being adopted because of better performance, cost, size, fault-tolerance and power consumption. In this paper we present an approach for the automatic software functionality assignment to multicore distributed architectures. We consider that the systems use the AUTomotive Open System ARchitecture (AUTOSAR). The functionality is modeled as a set of software components composed of subtasks, called runnables, in AUTOSAR terminology. We have proposed a Simulated Annealing metaheuristic optimization that decides: the (i) mapping of software components to multicore ECUs, (ii) the assignment of runnables to the ECU cores, (iii) the clustering of runnables into tasks and (iv) the mapping of tasks to “OS-Applications” (used to isolate mixed safety-criticality functions). We are interested to determine an implementation such that (1) the mapping constraints are satisfied, (2) the runnables are schedulable and (3) they are spatially and temporally isolated if they have different safety-criticality levels, (4) the overall communication bandwidth is minimized and (5) the utilization of the cores and ECUs is balanced. The proposed approach was evaluated on three realistic case studies.

@inproceedings{Maticu:2016aa,
  author = {Florin Maticu and Paul Pop and Axbrink Christian and Islam Mafijul},
  title = {Automatic functionality assignment to AUTOSAR multicore distributed architectures},
  booktitle = {SAE 2016 World Congress and Exhibition},
  publisher = {Society of Automotive Engineers},
  year = {2016},
  doi = {10.4271/2016-01-0041},
  url = {http://www.sae.org/congress/2016/}
}

In this paper, we are interested in the synthesis of fault-tolerant architectures for flow-based microfluidic biochips, which use microvalves and channels to run biochemical applications. The growth rate of device integration in flow-based microfluidic biochips is scaling faster than Moore's law. This increase in fabrication complexity has led to an increase in defect rates during the manufacturing, thereby motivating the need to improve the yield, by designing these biochips such that they are fault tolerant. We propose an approach based on a Greedy Randomized Adaptive Search Procedure (GRASP) for the synthesis of fault-tolerant biochip architectures. Our approach optimizes the introduction of redundancy within a given unit cost budget, such that, the biochemical application can successfully complete its execution within its deadline, even in the presence of faults, and the yield is maximized. The proposed algorithm has been evaluated using several benchmarks and compared to the results of a Simulated Annealing metaheuristic.

@inproceedings{Eskesen:2016ab,
  author = {Morten Chabert Eskesen and Paul Pop and Seetal Potluri},
  title = {Architecture Synthesis for Cost-Constrained Fault-Tolerant Flow-based Biochips},
  booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe},
  publisher = {IEEE},
  year = {2016},
  url = {https://www.date-conference.com/}
}

Microfluidic biochips are replacing the conventional biochemical analyzers integrating the necessary functions on-chip. We are interested in flow-based biochips, where a continuous flow of liquid is manipulated using integrated microvalves, controlled from external pressure sources via off-chip control pins. Recent research has addressed the physical design of such biochips. However, such research has so far ignored the pin-count, which rises with the increase in the number of microvalves. Given a biochip architecture and a biochemical application, we propose an algorithm for reducing the number of control pins required to run the application. The proposed algorithm has been evaluated using several benchmarks.

@inbook{Schneider:2016aa,
  author = {Schneider, {Alexander R{\"u}diger} and Paul Pop and Jan Madsen},
  title = {A Pin-Count Reduction Algorithm for Flow-Based Microfluidic Biochips},
  booktitle = {Collection of papers presented at the 18th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2016)},
  publisher = {IEEE},
  year = {2016},
  doi = {10.1109/DTIP.2016.7514873},
  url = {http://dx.doi.org/10.1109/DTIP.2016.7514873}
}

Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate onchip all the necessary functions for biochemical analysis using microfluidics. The digital microfluidic biochips are based on the manipulation of liquids not as a continuous flow, but as discrete droplets on an array of electrodes. Microfluidic operations, such as transport, mixing, split, are performed on this array by routing the corresponding droplets on a series of electrodes. Several approaches have been proposed for the compilation of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determine the allocation, resource binding, scheduling, placement and routing of the operations in the application. To simplify the compilation problem, researchers have assumed an abstract droplet size of one electrode. However, the droplet size abstraction is not realistic and it impacts negatively the execution of the biochemical application, leading in most cases to its failure. Hence the existing compilation approaches have to be revisited to consider the size of the droplets. In this paper we take the first step towards a droplet size-aware compilation by proposing a routing algorithm that considers the droplet size. Our routing algorithm is developed for a novel digital microfluidic biochip architecture based on Active Matrix Electrowetting on Dielectric, which uses a thin film transistor array for the electrodes. We also implement a simulator that allows us to perform the needed adaptations and to validate the proposed routing algorithm.

@inproceedings{Alistar:2015ab,
  author = {Mirela Alistar and Paul Pop},
  title = {Towards droplet size-aware biochemical application compilation for AM-EWOD biochips},
  booktitle = {Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)},
  publisher = {IEEE},
  year = {2015}
}

Ethernet is a low-cost communication solution offering high transmission speeds. Although its applications extend beyond computer networking, Ethernet is not suitable for real-time and safety-critical systems. To alleviate this, several real-time Ethernet-based communication protocols have been proposed, such as TTEthernet, which is the focus of this paper. TTEthernet is suitable for mixed-criticality systems both in the safety and temporal domain. TTEthernet offers three traffic classes: static time-triggered (TT) traffic, dynamic traffic with bounded transmission rate (called "Rate Constrained", RC), and unbounded dynamic traffic ("Best-Effort", BE). In this paper we propose a novel worst-case end-to-end delay analysis of the RC traffic for TTEthernet systems. The proposed technique considerably reduces the pessimism of the analysis, compared to existing approaches. We have evaluated the new analysis using several test cases.

@inproceedings{Tamas-Selicean:2015ac,
  author = {Domitian Tamas-Selicean and Paul Pop and Wilfried Steiner},
  title = {Timing Analysis of Rate Constrained Traffic for the TTEthernet Communication Protocol},
  booktitle = {International Symposium On Real-time Computing (ISORC)},
  publisher = {IEEE},
  year = {2015},
  doi = {10.1109/ISORC.2015.32},
  url = {http://www.isorc2015.org/}
}

In this paper we propose a system-level synthesis for MPSoCs that integrates multiple Application Specific Instruction Set Processors (ASIPs). Each ASIP is customized for a specific set of tasks. The system-level synthesis is responsible for assigning the tasks to the ASIPs, exploring different platform alternatives. We can allocate tasks to the different ASIPs and determine if the applications are schedulable only knowing the worst-case execution time (WCET) of each task. We can estimate the WCET only after establishing the micro-architecture of the ASIP. At the same time, an ASIP micro-architecture can be derived only knowing the assignment of tasks to ASIP. To address this circular dependency, we propose an Uncertainty Model for the WCETs, which captures the performance of tasks running on a range of possible ASIP implementations. We propose a novel stochastic schedulability analysis to evaluate each multi-ASIP platform. We use an Evolutionary Algorithm-based approach to explore the design space of macro-architecture possibilities and we evaluate it using real case studies.

@article{Micconi:2015ab,
  author = {Laura Micconi and Jan Madsen and Paul Pop},
  title = {System-level synthesis of multi-ASIP platforms using an uncertainty model},
  journal = {Integration},
  publisher = {Elsevier},
  year = {2015},
  doi = {10.1016/j.vlsi.2015.07.006}
}

Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate all the necessary functions for biochemical analysis. The digital microfluidic biochips are based on the manipulation of liquids not as a continuous flow, but as discrete droplets. Several approaches have been proposed for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determine the allocation, resource binding, scheduling, placement and routing of the operations in the application. Researchers have assumed that each biochemical operation in an application is characterized by a worst-case execution time (wcet). However, during the execution of the application, due to variability and randomness in biochemical reactions, operations may finish earlier than their wcetswcets, resulting in unexploited slack in the schedule. In this paper, we first propose an online synthesis strategy that re-synthesizes the application at runtime when operations experience variability in their execution time, exploiting thus the slack to obtain shorter application completion times. We also propose a quasi-static synthesis strategy that determines offline a database of alternative implementations. During the execution of the application, several implementations are selected based on the current execution scenario with operation execution time variability. The proposed strategies have been evaluated using several benchmarks and compared to related work.

@article{Alistar:2015ac,
  author = {Mirela Alistar and Paul Pop},
  title = {Synthesis of Biochemical Applications on Digital Microfluidic Biochips with Operation Execution Time Variability},
  journal = {Integration, the VLSI Journal},
  publisher = {Elsevier},
  year = {2015},
  doi = {10.1016/j.vlsi.2015.02.004}
}

Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate all the necessary functions for biochemical analysis. The digital microfluidic biochips are based on the manipulation of liquids not as a continuous flow, but as discrete droplets. Researchers have proposed approaches for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determine the allocation, resource binding, scheduling, placement and routing of the operations in the application. During the execution of a bioassay, operations could experience transient errors (e.g., erroneous droplet volumes), thus impacting negatively the correctness of the application. Researchers have proposed fault-tolerance approaches, which apply predetermined recovery actions at the moment when errors are detected. In this paper, we propose an online recovery strategy, which decides during the execution of the biochemical application the introduction of the redundancy required for fault-tolerance. We consider both time redundancy, i.e., re-executing erroneous operations, and space redundancy, i.e., creating redundant droplets for fault-tolerance. Error recovery is performed such that the number of transient errors tolerated is maximized and the timing constraints of the biochemical application are satisfied. The proposed redundancy optimization approach has been evaluated using several benchmarks.

@article{Alistar:2015aa,
  author = {Mirela Alistar and Paul Pop and Jan Madsen},
  title = {Redundancy Optimization for Error Recovery in Digital Microfluidic Biochips},
  journal = {Design Automation for Embedded Systems},
  publisher = {Springer Netherlands},
  year = {2015},
  doi = {10.1007/s10617-014-9157-2}
}

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. In this paper we are interested in flow-based biochips, in which the fluidic flow manipulated using integrated microvalves, which are controlled from external pressure sources, connected to “control pins”. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. The current practice is to design these biochips by hand in drawing tools such as AutoCAD, and to program them manually by individually controlling each valve. Recent research has proposed top-down physical synthesis Computer- Aided Design tools, and programming languages and compilation techniques to automatically derive the control signals for the valve actuations. However, researchers have so far assumed that the number of ports used to drive the valves (control pins) is unlimited, which has resulted in very expensive, bulky and energy consuming off-chip control and infeasible control routes in the biochip control layer. In this paper, we propose a methodology to reduce the number of control pins required to run a biochemical application. We focus on the compilation task, where the strategy is to delay operations, without missing their deadlines, such that the sharing of control signals is maximized. The evaluation shows a significant reduction in the number of control pins required.

@inproceedings{Raagaard:2015aa,
  author = {Michael Lander Raagaard and Paul Pop},
  title = {Pin Count-Aware Biochemical Application Compilation for mVLSI Biochips},
  booktitle = {Symposium on Design Test Integration and Packaging of MEMS/MOEMS (DTIP)},
  publisher = {IEEE},
  year = {2015},
  doi = {10.1109/DTIP.2015.7161026}
}

Microfluidic biochips are replacing the conventional biochemical analyzers by integrating all the necessary functions for biochemical analysis using microfluidics. Biochips are used in many application areas, such as, in vitro diagnostics, drug discovery, biotech and ecology. The focus of this paper is on continuous-flow biochips, where the basic building block is a microvalve. By combining these microvalves, more complex units such as mixers, switches, multiplexers can be built, hence the name of the technology, “microfluidic Very Large-Scale Integration” (mVLSI). A roadblock in the deployment of microfluidic biochips is their low reliability and lack of test techniques to screen defective devices before they are used for biochemical analysis. Defective chips lead to repetition of experiments, which is undesirable due to high reagent cost and limited availability of samples. This paper presents the state-of-the-art in the mVLSI platforms and emerging research challenges in the area of continuous-flow microfluidics, focusing on testing techniques and fault-tolerant design.

@inproceedings{Araci:2015aa,
  author = {Ismail Emre Araci and Paul Pop and Krishnendu Chakrabarty},
  title = {Microfluidic Very Large-Scale Integration for Biochips: Technology, Testing and Fault-Tolerant Design},
  booktitle = {Proceedings of the European Test Symposium},
  publisher = {IEEE},
  year = {2015},
  doi = {10.1109/ETS.2015.7138736},
  url = {http://www.ieee.org/conferences\_events/conferences/conferencedetails/index.html?Conf\_ID=35553}
}

This chapter presents an introduction to the microfluidics field and microfluidic biochips. We discuss the main fluid propulsion principles used by modern microfluidic platforms, with a focus on “digital” microfluidic biochips, which are the topic of this book. Digital microfluidic biochips manipulate the fluids as small “droplets” using electrokinetics, i.e., electrowetting-on-dielectric. Several application areas for biochips are discussed, and the motivation behind the work presented in this book is introduced. At the end of the chapter, we outline the structure of the book and an overview of the topics covered.

@inbook{Pop:2015ab,
  author = {Paul Pop and Mirela Alistar and Elena Stuart and Jan Madsen},
  title = {Introduction},
  booktitle = {Fault-Tolerant Digital Microfluidic Biochips},
  publisher = {Springer},
  year = {2015},
  doi = {10.1007/978-3-319-23072-6\_1}
}

The focus of this paper is on continuous-flow biochips, where the basic building block is a microvalve. By combining these microvalves, more complex units such as mixers, switches, multiplexers can be built, hence the name of the technology, “microfluidic Very Large Scale Integration” (mVLSI). Biochips are currently being designed manually using tools such as AutoCAD. Physical defects can be introduced during the fabrication process, which reduces the yield, and may lead to the failure of the biochemical application. Failure is costly because of the need to redo lengthy experiments, using expensive reagents and often hard-to-obtain samples, and can be safety critical (endangering human life), e.g., for important diagnostic procedures (screening for cancer). Researchers have started to propose fault models and test techniques for mVLSI biochips. To increase the yield, and to potentially also prevent the failure during the operation of the biochip, we advocate the use of fault-tolerant biochip design. The vision is to provide application fault-tolerance at run-time (online), detecting the faults as they appear, and reconfiguring the application. However, in this paper our assumption is that the faults are detected during testing, and that the operation of the biochip is reconfigured offline (at design time) to avoid the faults. We are interested to introduce redundancy such that the applications can still successfully run on a defective biochip. Redundancy is the addition of extra resources, normally not needed for correct operation, to be used for fault-tolerance.

@inproceedings{Pop:2015ad,
  author = {Paul Pop},
  title = {Flow-Based Biochips: Fault-Tolerant Design and Error Recovery},
  booktitle = {Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society},
  publisher = {IEEE},
  year = {2015}
}

Many safety-critical real-time applications are implemented using distributed architectures, composed of heterogeneous processing elements (PEs) interconnected in a network. In this paper, we are interested in the TTEthernet protocol, which is a deterministic, synchronized and congestion-free network protocol based on the IEEE 802.3 Ethernet standard and compliant with ARINC 664p7. TTEthernet supports three types of traffic: static time-triggered (TT) traffic and dynamic traffic, which is further subdivided into Rate Constrained (RC) traffic that has bounded end-to-end latencies, and Best-Effort (BE) traffic, for which no timing guarantees are provided. TTEthernet offers spatial separation through the concept of virtual links (VLs), and temporal separation, through schedule tables for TT messages and bandwidth allocation for RC messages. Given a set of PEs, we are interested to determine a fault-tolerant network topology, consisting of redundant physical links and network switches, such that the architecture cost is minimized, the applications are fault-tolerant to a given number of permanent faults occurring in the communication network, and the timing constraints of the TT and RC messages are satisfied. Deciding on a fault-tolerant topology means (i) deciding on the number of network switches, (ii) the physical links and the network topology, (iii) the routing of VLs on top of the physical network, (iv) the assignment of frames to VLs and (v) the schedule tables for the TT frames. We propose a Simulated Annealing meta-heuristic to solve this optimization problem. The proposed approach has been evaluated using a synthetic benchmark and a space case study, based on the Orion Crew Exploration Vehicle.

@inproceedings{Gavrilut:2015aa,
  author = {Voica Gavrilut and Domitian Tamas-Selicean and Paul Pop},
  title = {Fault-Tolerant Topology Selection for TTEthernet Networks},
  booktitle = {Proceedings of the Safety and Reliability of Complex Engineered Systems Conference},
  publisher = {CRC Press, Taylor \& Francis Group},
  year = {2015},
  url = {https://www.sintef.no/globalassets/project/hfc/documents/esrel2015\_program\_6\_sept\_v2.pdf}
}

Many safety-critical real-time applications are implemented using distributed architectures, composed of heterogeneous processing elements interconnected in a network. Our focus in this paper is on the TTEthernet protocol, a deterministic, synchronized and congestion-free network protocol based on the Ethernet standard and compliant with the ARINC 664 Specification Part 7. TTEthernet is highly suitable for safety-critical real-time applications since it offers separation for messages using the concept of virtual links and supports three time-criticality classes: Time-Triggered (TT), Rate-Constrained (RC) and Best-Effort. In this paper we are interested in the design optimization of TTEthernet networks used to transmit real-time application messages. Given the set of TT and RC messages, and the topology of the network, our approach optimizes the packing of messages in frames, the assignment of frames to virtual links, the routing of virtual links and the TT static schedules, such that all frames are schedulable and the worst-case end-to-end delay of the RC messages is minimized. We propose a Tabu Search-based metaheuristic for this optimization problem. The proposed algorithm has been evaluated using several benchmarks.

@article{Tamas-Selicean:2015aa,
  author = {Domitian Tamas-Selicean and Paul Pop and Wilfried Steiner},
  title = {Design Optimization of TTEthernet-based Distributed Real-Time Systems},
  journal = {Real-Time Systems Journal},
  publisher = {Springer Netherlands},
  year = {2015},
  doi = {10.1007/s11241-014-9214-8}
}

In this article, we are interested in implementing mixed-criticality real-time embedded applications on a given heterogeneous distributed architecture. Applications have different criticality levels, captured by their Safety-Integrity Level (SIL), and are scheduled using static-cyclic scheduling. According to certification standards, mixed-criticality tasks can be integrated onto the same architecture only if there is enough spatial and temporal separation among them. We consider that the separation is provided by partitioning, such that applications run in separate partitions, and each partition is allocated several time slots on a processor. Tasks of different SILs can share a partition only if they are all elevated to the highest SIL among them. Such elevation leads to increased development costs, which increase dramatically with each SIL. Tasks of higher SILs can be decomposed into redundant structures of lower SIL tasks. We are interested to determine (i) the mapping of tasks to processors, (ii) the assignment of tasks to partitions, (iii) the decomposition of tasks into redundant lower SIL tasks, (iv) the sequence and size of the partition time slots on each processor, and (v) the schedule tables, such that all the applications are schedulable and the development costs are minimized. We have proposed a Tabu Search-based approach to solve this optimization problem. The proposed algorithm has been evaluated using several synthetic and real-life benchmarks.

@article{Tamas-Selicean:2015ab,
  author = {Domitian Tamas-Selicean and Paul Pop},
  title = {Design Optimization of Mixed-Criticality Real-Time Systems},
  journal = {ACM Transaction on Embedded Computing},
  publisher = {Association for Computing Machinery},
  year = {2015},
  doi = {10.1145/2700103}
}

This article is a tutorial on continuous-flow biochips where the basic building blocks are microchannels, and microvalves, and by combining them, more complex units such as mixers, switches, and multiplexers can be built. It also presents the state of the art in flow-based biochip technology and emerging research challenges in the areas of physical design and testing techniques.

@article{Pop:2015af,
  author = {Paul Pop and Ismail Emre Araci and Krishnendu Chakrabarty},
  title = {Continuous-Flow Biochips: Technology, Physical Design Methods and Testing},
  journal = {IEEE Design and Test},
  publisher = {IEEE},
  year = {2015},
  doi = {10.1109/MDAT.2015.2438152}
}

@inproceedings{Pop:2015ag,
  author = {Pop, Paul and Ho, Tsung-Yi and Chakrabarty, Krishnendu and Grover, William H.},
  title = {Continuous-flow biochips: Current platforms and emerging research challenges},
  booktitle = {28th International Conference on VLSI Design},
  publisher = {IEEE Computer Society Press},
  year = {2015},
  doi = {10.1109/VLSID.2015.120},
  url = {http://vlsidesignconference.org/BACKUP/vlsi2015\_Website-Backup\%2812.May.15\%29/}
}

@misc{Pop:2014aa,
  author = {Paul Pop and Jan Madsen and Kasper Understrup and Mirela Alistar and Minhass, {Wajid Hassan} and Ulrich Kr{\"u}hne},
  title = {Programming language and tools for Multipurpose Lab-on-a-Chip Platforms},
  year = {2014},
  url = {http://selectbiosciences.com/conferences/index.aspx?conf=loacec2014}
}

This paper focuses on the optimization of the TTEthernet communication protocol, which offers three traffic classes: time-triggered (TT), sent according to static schedules, rate-constrained (RC) that has bounded end-to-end latency, and best-effort (BE), the classic Ethernet traffic, with no timing guarantees. In our earlier work we have proposed an optimization approach named DOTTS that performs the routing, scheduling and packing / fragmenting of TT and RC messages, such that the TT and RC traffic is schedulable. Although backwards compatibility with classic Ethernet networks is one of TTEthernet’s strong points, there is little research on this topic. However, in this paper, we extend our DOTTS optimization approach to optimize TTEthernet networks, such that not only the TT and RC messages are schedulable, but we also maximize the available bandwidth for BE messages. The proposed optimization has been evaluated on a space application case study.

@inproceedings{Tamas-Selicean:2014ab,
  author = {Domitian Tamas-Selicean and Paul Pop},
  title = {Optimization of TTEthernet Networks to Support Best-Effort Traffic},
  booktitle = {WiP Proceedings of Emerging Technologies and Factory Automation},
  publisher = {IEEE},
  year = {2014},
  doi = {10.1109/ETFA.2014.7005256},
  url = {http://www.etfa2014.org/}
}

In this paper we propose a new Tabu Search-based design optimization strategy for mixed-criticality systems implementing hard and soft real-time applications on the same platform. Our proposed strategy determined an implementation such that all hard real-time applications are schedulable and the quality of service of the soft real-time tasks is maximized. We have evaluated our strategy using an aerospace case study.

@inproceedings{Tamas-Selicean:2014ac,
  author = {Domitian Tamas-Selicean and Paul Pop},
  title = {Optimization of Partitioned Architectures to Support Soft Real-Time Applications},
  booktitle = {Pacific Rim International Symposium on Dependable Computing (PRDC)},
  publisher = {IEEE},
  year = {2014},
  url = {http://prdc.dependability.org/PRDC2014/index.html}
}

Several approaches have been proposed for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determine the allocation, resource binding, scheduling, placement and routing of the operations in the application. Researchers have assumed that each biochemical operation in an application is characterized by a worst-case execution time (wcet). However, during the execution of the application, due to variability and randomness in biochemical reactions, operations may finish earlier than their wcets. In this paper we propose an online synthesis strategy that re-synthesizes the application at runtime when operations experience variability in their execution time, obtaining thus shorter application execution times. The proposed strategy has been evaluated using several benchmarks.

@inproceedings{Alistar:2014ab,
  author = {Mirela Alistar and Paul Pop},
  title = {Online Synthesis for Operation Execution Time Variability on Digital Microfluidic Biochips},
  booktitle = {International Symposium on Integrated Circuits},
  publisher = {IEEE},
  year = {2014},
  url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7005969}
}

Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate onchip all the necessary functions for biochemical analysis using microfluidics. The digital microfluidic biochips are based on the manipulation of liquids not as a continuous flow, but as discrete droplets on an array of electrodes. Microfluidic operations, such as transport, mixing, split, are performed on this array by routing the corresponding droplets on a series of electrodes. Researchers have proposed several approaches for the synthesis of digital microfluidic biochips. All previous work assumes that the biochip architecture is given, and consider a rectangular shape for the electrode array. However, non-regular application-specific architectures are common in practice. In this paper, we are interested in determining a placement of operations for application-specific biochips, such that the application completion time is minimized. The proposed algorithm has been evaluated using several benchmarks.

@inproceedings{Alistar:2013ab,
  author = {Mirela Alistar and Paul Pop and Jan Madsen},
  title = {Operation placement for application-specific digital microfluidic biochips},
  booktitle = {Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)},
  publisher = {IEEE},
  year = {2013},
  url = {http://cmp.imag.fr/conferences/dtip/dtip2013/}
}

In this paper we are interested in deriving a distributed platform, composed of heterogeneous processing elements, targeted to applications that have strict timing constraints. We consider that the platform may use multiple Application Specific Instruction Set Processors (ASIPs). An ASIP is synthesized and tuned for a specific set of tasks (i.e., a task cluster). During design space exploration (DSE), we evaluate each platform solution visited in terms of its cost and performance, i.e., its ability to execute the applications such that they meet their timing constraints. To determine if the applications are schedulable, we have to know the worst-case execution time (WCET) of each task. However, we can determine the WCETs only after the ASIPs are synthesized, which is time consuming and therefore cannot be done during DSE. To address this circular dependency (the ASIPs depend on the task clustering, and the WCETs of tasks, used to determine schedulability, depend on how ASIPs are synthesized), we propose an uncertainty model for the WCETs, which captures the range of possible ASIP implementations. Based on this model, we synthesize a multi-ASIP platform, such that the applications have a high chance of being schedulable and the cost constraints imposed on the platform are fulfilled. We propose an Evolutionary Algorithm-based approach, which uses a novel stochastic schedulability analysis to solve this optimization problem. The proposed approach has been evaluated using several benchmarks.

@inproceedings{Micconi:2013ab,
  author = {Laura Micconi and Deepak Gangadharan and Paul Pop and Jan Madsen},
  title = {Multi-ASIP Platform Synthesis for Real-Time Applications},
  booktitle = {International Symposium on Industrial Embedded Systems},
  publisher = {IEEE},
  year = {2013},
  doi = {10.1109/SIES.2013.6601471},
  url = {http://dx.doi.org/10.1109/SIES.2013.6601471}
}

In this paper, we propose a technique to synthesize a cost-efficient distributed platform consisting of multiple Application Specific Instruction Set Processors (multi-ASIPs) running applications with strict timing constraints. Multi-ASIP platform synthesis is a non-trivial task for two reasons. Firstly, we need to know the WCET of tasks in target applications to derive platforms (including synthesized ASIPs) in which the tasks are schedulable. However, the WCET of tasks can be known only after the ASIPs are synthesized. We break this circular dependency by using a probability distribution of the WCET of a task (further referred to as the WCET uncertainty model), which takes into account the underlying microarchitectural configurations for the ASIP implementation. Secondly, the datapath area of the multi-ASIPs synthesized is an important design factor that contributes significantly towards the overall cost of the platform. We propose an area estimation model and a WCET uncertainty model that consider the effect of task datapath similarity. Based on these two models, we support the designer in exploring cost/performance trade-offs during the platform synthesis. We propose an Evolutionary Algorithm-based approach to solve this multiobjective optimization problem. The proposed approach has been evaluated using several benchmarks and it provides a number of multi-ASIP platform solutions exploring the trade-offs in the cost/performance design space.

@inproceedings{Gangadharan:2013aa,
  author = {Deepak Gangadharan and Laura Micconi and Paul Pop and Jan Madsen},
  title = {Multi-ASIP Platform Synthesis for Event-Triggered Applications with Cost/Performance Trade-offs},
  booktitle = {International Conference on Embedded and Real-Time Computing Systems and Applications},
  publisher = {IEEE},
  year = {2013},
  doi = {10.1109/RTCSA.2013.6732228},
  url = {http://dx.doi.org/10.1109/RTCSA.2013.6732228}
}

Microfluidic biochips represent an alternative to conventional biochemical analyzers. A digital biochip manipulates liquids not as continuous flow, but as discrete droplets on a two-dimensional array of electrodes. Several electrodes are dynamically grouped to form a virtual device, on which operations are executed by moving the droplets. So far, researchers have ignored the locations of droplets inside devices, considering that all the electrodes forming the device are occupied throughout the operation execution. In this article, we consider a droplet-aware execution of microfluidic operations, which means that we know the exact position of droplets inside the modules at each time-step. We propose a Tabu Search-based metaheuristic for the synthesis of digital biochips with droplet-aware operation execution. Experimental results show that our approach can significantly reduce the application completion time, allowing us to use smaller area biochips and thus reduce costs.

@article{Maftei:2013aa,
  author = {Elena Maftei and Paul Pop and Jan Madsen},
  title = {Module-Based Synthesis of Digital Microfluidic Biochips with Droplet-Aware Operation Execution},
  journal = {ACM Journal on Emerging Technologies in Computing Systems},
  publisher = {Association for Computing Machinery},
  year = {2013},
  doi = {10.1145/2422094.2422096},
  url = {http://dx.doi.org/10.1145/2422094.2422096}
}

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. In this paper we are interested in flow-based biochips, in which the fluidic flow is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. Such biochips are becoming increasingly complex, with thousands of components, but are still designed manually using a bottom-up full-custom design approach, which is extremely labor intensive and error prone. In this paper, we present an Integrated Development Environment (IDE), which addresses (i) schematic capture of the biochip architecture and biochemical application, (ii) logic simulation of an application running on a biochip, and is able to integrate the high level synthesis tasks we have developed for the top-down design of flow-based biochips. We show how the IDE can be used to design biochips for several applications.

@inproceedings{Schmidt:2013aa,
  author = {Schmidt, {Morten Foged} and Minhass, {Wajid Hassan} and Paul Pop and Jan Madsen},
  title = {Modeling and Simulation Framework for Flow-Based Microfluidic Biochips},
  booktitle = {Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)},
  publisher = {IEEE},
  year = {2013},
  url = {http://cmp.imag.fr/conferences/dtip/dtip2013/}
}

@inproceedings{Pop:2013aa,
  author = {Pop, Paul and Leonidas Tsiopoulos and Sebastian Voss and Oscar Slotosch and Christoph Ficek and Ulrik Nyman and Alejandra Ruiz Lopez},
  title = {Methods and tools for reducing certification costs of mixed-criticality applications on multi-core platforms: the RECOMP approach},
  booktitle = {Workshop on Industry-Driven Approaches for Cost-effective Certification of Safety-Critical, Mixed-Criticality Systems (part of the Design, Automation and Test in Europe Conference)},
  year = {2013}
}

This work proposes a hierarchical Design Space Exploration (DSE) for the design of multi-processor platforms targeted to specific applications with strict timing and area constraints. In particular, it considers platforms integrating multiple Application Specific Instruction Set Processors (ASIPs) and each ASIP is automatically synthesized and tuned for a specific set of tasks. The definition of the platform (number of processors and their interconnection) and of the micro-architecture of each single ASIP are tightly coupled. Tasks can be allocated to the different ASIPs only knowing their performance and therefore the ASIP micro-architecture. At the same time an ASIP can be derived only knowing the functionality that it has to implement, i.e. the tasks that are assigned. We break this circular dependency with an iterative hierarchical DSE, applied at platform and micro-architecture level. We evaluate different platforms and micro-architecture alternatives to find a multi-ASIP platform targeted to the input application and able to meet the design constraints. We evaluate our design flow using a MJPEG encoder application.

@inproceedings{Micconi:2013aa,
  author = {Laura Micconi and Rosilde Corvino and Deepak Gangadharan and Jan Madsen and Paul Pop and Lech Jozwiak},
  title = {Hierarchical DSE for multi-ASIP platforms},
  booktitle = {Mediterranean Conference on Embedded Computing},
  publisher = {IEEE},
  year = {2013},
  doi = {10.1109/MECO.2013.6601379},
  url = {http://dx.doi.org/10.1109/MECO.2013.6601379}
}

The current trend in spacecraft computing is to integrate applications of different criticality levels on the same platform using no separation. This approach increases the complexity of the development, verification and integration processes, with an impact on the whole system life cycle. Researchers at ESA and NASA advocated for the use of partitioned architecture to reduce this complexity. Partitioned architectures rely on platform mechanisms to provide robust temporal and spatial separation between applications. Such architectures have been successfully implemented in several industries, such as avionics and automotive. In this paper we investigate the challenges of developing and the benefits of integrating a scientific instrument, namely a Fourier Transform Spectrometer, in such a partitioned architecture.

@inproceedings{Tamas-Selicean:2013aa,
  author = {Domitian Tamas-Selicean and D. Keymeulen and D. Berisford and R. Carlson and K. Hand and Paul Pop and W. Wadsworth and R. Levy},
  title = {Fourier Transform Spectrometer Controller for Partitioned Architectures},
  booktitle = {IEEE Aerospace Conference},
  publisher = {IEEE},
  year = {2013},
  doi = {10.1109/AERO.2013.6496969},
  url = {http://dx.doi.org/10.1109/AERO.2013.6496969}
}

This tutorial will first provide an overview of typical bio-molecular applications (market drivers) such as immunoassays, DNA sequencing, clinical chemistry, etc. Next, microarrays and various microfluidic platforms will be discussed. The next part of the tutorial will focus on electro-wetting-based digital micro-fluidic biochips. The key idea here is to manipulate liquids as discrete droplets. A number of case studies based on representative assays and laboratory procedures will be interspersed in appropriate places throughout the tutorial. Basic concepts in micro-fabrication techniques will also be discussed. Attendees will next learn about CAD and reconfiguration aspects of digital microfluidic biochips. Synthesis tools will be described to map assay protocols from the lab bench to a droplet-based microfluidic platform and generate an optimized schedule of bioassay operations, the binding of assay operations to functional units, and the layout and droplet-flow paths for the biochip. The role of the digital microfluidic platform as a “programmable and reconfigurable processor” for biochemical applications will be highlighted. Cyber-physical integration using low-cost sensors and adaptive control, software will be highlighted. Cost-effective testing techniques will be described to detect faults after manufacture and during field operation. On-line and off-line reconfiguration techniques will be presented to easily bypass faults once they are detected. The problem of mapping a small number of chip pins to a large number of array electrodes will also be covered. With the availability of these tools, chip users and chip designers will be able to concentrate on the development and chip-level adaptation of nano-scale bioassays (higher productivity), leaving implementation details to CAD tools.

@inproceedings{Ho:2013aa,
  author = {Tsung-Yi Ho and Juinn-Dar Huang and Paul Pop},
  title = {Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration},
  booktitle = {International SoC Conference (SOCC)},
  publisher = {IEEE},
  year = {2013},
  doi = {10.1109/SOCC.2013.6749708},
  url = {http://dx.doi.org/10.1109/SOCC.2013.6749708}
}

In this paper we are interested in flow-based microfluidic biochips, which are able to integrate the necessary functions for biochemical analysis on-chip. In these chips, the flow of liquid is manipulated using integrated microvalves. By combining severalmicrovalves, more complex units, such asmicropumps, mixers, and multiplexers, can be built. In this paper we propose, for the first time to our knowledge, a top-down control synthesis framework for the flow-based biochips. Starting from a given biochemical application and a biochip architecture, we synthesize the control logic that is used by the biochip controller to automatically execute the biochemical application. We also propose a control pin count minimization scheme aimed at efficiently utilizing chip area, reducing macro-assembly around the chip and enhancing chip scalability. We have evaluated our approach using both real-life applications and synthetic benchmarks.

@inproceedings{Minhass:2013aa,
  author = {Minhass, {Wajid Hassan} and Paul Pop and Jan Madsen and Tsung-Yi Ho},
  title = {Control Synthesis for the Flow-Based Microfluidic Large-Scale Integration Biochips},
  booktitle = {Asia and South Pacific Design Automation Conference},
  publisher = {IEEE},
  year = {2013},
  doi = {10.1109/ASPDAC.2013.6509597},
  url = {http://dx.doi.org/10.1109/ASPDAC.2013.6509597}
}

@misc{Alistar:2013ac,
  author = {Mirela Alistar and Paul Pop and Jan Madsen},
  title = {Biochemical Application Compilation and Architecture Synthesis for Fault-Tolerant Digital Microfluidic Biochips},
  year = {2013 \color{red}\textbf{Best Poster Award}}
}

This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It presents an overview of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program. The paper briefly presents the results of our analysis of the main challenges to be faced in the design of such heterogeneous MPSoCs. It explains which system, design, and electronic design automation (EDA) concepts seem to be adequate to address the challenges and solve the problems. Finally, it discusses the ASAM design-flow, its main stages and tools and their application to a real-life case study.

@article{Jozwiak:2013aa,
  author = {Lech Jozwiak and Menno Lindwer and Rosilde Corvino and Paolo Meloni and Laura Micconi and Jan Madsen and Erkan Diken and Deepak Gangadharan and Roel Jordans and Sebastiano Pomata and Paul Pop and Giuseppe Tuveri and Luigi Raffo and Giuseppe Notarangelo},
  title = {ASAM: Automatic architecture synthesis and application mapping},
  journal = {Microprocessors and Microsystems},
  publisher = {Elsevier},
  year = {2013},
  doi = {http://dx.doi.org/10.1016/j.micpro.2013.08.006},
  url = {http://dx.doi.org/10.1016/j.micpro.2013.08.006}
}

Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate onchip all the necessary functions for biochemical analysis using microfluidics. The digital microfluidic biochips are based on the manipulation of liquids not as a continuous flow, but as discrete droplets on an array of electrodes. Microfluidic operations, such as transport, mixing, split, are performed on this array by routing the corresponding droplets on a series of electrodes. Researchers have proposed several approaches for the synthesis of digital microfluidic biochips. All previous work assumes that the biochip architecture is given, and most approaches consider a rectangular shape for the electrode array. However, non-regular application-specific architectures are common in practice. Hence, in this paper, we propose an approach to the application-specific architecture synthesis. Our approach can also help the designer to increase the yield by introducing redundant electrodes to tolerate permanent faults. The proposed architecture synthesis algorithm has been evaluated using several benchmarks.

@inproceedings{Alistar:2013aa,
  author = {Mirela Alistar and Paul Pop and Jan Madsen},
  title = {Application-specific fault-tolerant architecture synthesis for digital microfluidic biochips},
  booktitle = {Asia and South Pacific Design Automation Conference},
  year = {2013},
  doi = {10.1109/ASPDAC.2013.6509697},
  url = {http://dx.doi.org/10.1109/ASPDAC.2013.6509697}
}

Designs of flow-based microfluidic biochips are receiving much attention recently because they replace conventional biological automation paradigm and are able to integrate different biochemical analysis functions on a chip. However, as the design complexity increases, a flow-based microfluidic biochip needs more chip-integrated micro-valves, i.e., the basic unit of fluid-handling functionality, to manipulate the fluid flow for biochemical applications. Moreover, frequent switching of micro-valves results in decreased reliability. To minimize the valve-switching activities, we develop a network-flow based resource binding algorithm based on breadth-first search (BFS) and minimum cost maximum flow (MCMF) in architectural-level synthesis. The experimental results show that our methodology not only makes significant reduction of valve-switching activities but also diminishes the application completion time for both real-life applications and a set of synthetic benchmarks.

@inproceedings{Tseng:2013aa,
  author = {Kai-Han Tseng and Sheng-Chi You and Minhass, {Wajid Hassan} and Tsung-Yi Ho and Paul Pop},
  title = {A network-flow based valve-switching aware binding algorithm for flow-based microfluidic biochips},
  booktitle = {Asia and South Pacific Design Automation Conference (ASP-DAC)},
  publisher = {IEEE},
  year = {2013},
  doi = {10.1109/ASPDAC.2013.6509598},
  url = {http://dx.doi.org/10.1109/ASPDAC.2013.6509598}
}

In this paper we are interested in the timing analysis of mixed-criticality embedded real-time applications mapped on distributed heterogeneous architectures. Mixedcriticality tasks can be integrated onto the same architecture only if there is enough spatial and temporal separation among them. We consider that the separation is provided by partitioning, such that applications run in separate partitions, and each partition is allocated several time slots on a processor. Each partition can have its own scheduling policy. We are interested to determine the worst-case response times of tasks scheduled in partitions using fixedpriority preemptive scheduling. We have extended the stateof- the-art algorithms for schedulability analysis to take into account the partitions. The proposed algorithm has been evaluated using several synthetic and real-life benchmarks.

@inproceedings{Marinescu:2012aa,
  author = {Marinescu, {Sorin Ovidiu} and Domitian Tamas-Selicean and Vlad Acretoaie and Paul Pop},
  title = {Timing Analysis of Mixed-Criticality Hard Real-Time Applications Implemented on Distributed Partitioned Architectures},
  booktitle = {Conference on Emerging Technologies Factory Automation},
  year = {2012},
  doi = {10.1109/ETFA.2012.6489720},
  url = {http://dx.doi.org/10.1109/ETFA.2012.6489720}
}

In this paper we address the mapping of mixedcriticality hard real-time applications on distributed embedded architectures. We assume that the architecture provides both spatial and temporal partitioning, thus enforcing enough separation between applications. With temporal partitioning, each application runs in a separate partition, and each partition is allocated several time slots on the processors where the application is mapped. The sequence of time slots for all the applications on a processor are grouped within a Major Frame, which is repeated periodically. We assume that the applications are scheduled using static-cyclic scheduling. We are interested to determine the task mapping to processors, and the sequence and size of the time slots within the Major Frame on each processor, such that the applications are schedulable. We have proposed a Tabu Search-based approach to solve this optimization problem. The proposed algorithm has been evaluated using several synthetic and real-life benchmarks.

@inproceedings{Tamas-Selicean:2012ac,
  author = {Domitian Tamas-Selicean and Paul Pop},
  title = {Task Mapping and Partition Allocation for Mixed-Criticality Real-Time Systems},
  booktitle = {Pacific Rim International Symposium on Dependable Computing (PRDC)},
  publisher = {IEEE},
  year = {2012},
  doi = {10.1109/PRDC.2011.42},
  url = {http://dx.doi.org/10.1109/PRDC.2011.42}
}

@misc{Minhass:2012ad,
  author = {Wajid Hassan Minhass and Paul Pop and Jan Madsen},
  title = {System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Large-Scale Integration Biochips},
  year = {2012}
}

@misc{Maftei:2012ac,
  author = {Elena Maftei and Paul Pop and Jan Madsen},
  title = {Synthesis of Digital Microfluidic Biochips with Reconfigurable Operation Execution},
  year = {2012}
}

In this paper we are interested in safety-critical distributed systems, composed of heterogeneous processing elements interconnected using the TTEthernet protocol. We address hard real-time mixed-criticality applications, which may have different criticality levels, and we focus on the optimization of the communication configuration. TTEthernet integrates three types of traffic: Time-Triggered (TT) messages, Event-Triggered (ET) messages with bounded end-to-end delay, also called Rate Constrained (RC) messages, and Best-Effort (BE) messages, for which no timing guarantees are provided. TT messages are transmitted based on static schedule tables, and have the highest priority. RC messages are transmitted if there are no TT messages, and BE traffic has the lowest priority. TT and RC traffic can carry safety-critical messages, while BE messages are non-critical. Mixed-criticality tasks and messages can be integrated onto the same architecture only if there is enough spatial and temporal separation among them. TTEthernet offers spatial separation for mixed-criticality messages through the concept of virtual links, and temporal separation, enforced through schedule tables for TT messages and bandwidth allocation for RC messages. Given the set of mixed-criticality messages in the system and the topology of the virtual links on which the messages are transmitted, we are interested to synthesize offline the static schedules for the TT messages, such that the deadlines for the TT and RC messages are satisfied, and the end-to-end delay of the RC traffic is minimized. We have proposed a Tabu Search-based approach to solve this optimization problem. The proposed algorithm has been evaluated using several benchmarks.

@inproceedings{Tamas-Selicean:2012ab,
  author = {Domitian Tamas-Selicean and Paul Pop and Wilfried Steiner},
  title = {Synthesis of Communication Schedules for TTEthernet-Based Mixed-Criticality Systems},
  booktitle = {International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)},
  publisher = {Association for Computing Machinery},
  year = {2012},
  doi = {10.1145/2380445.2380518},
  url = {http://dx.doi.org/10.1145/2380445.2380518}
}

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. In this paper we are interested in flow-based biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. We propose a constraint programming (CP) based approach for the synthesis of biochemical applications on flow-based microfluidic biochips. We use a sequencing graph to model the biochemical application and consider that the biochip architecture is given. We model the architecture using a topology graph. We are interested in synthesizing an implementation, consisting of binding and scheduling of the biochemical operations onto the components of the architecture, such that the resource and dependency constraints are satisfied and the application completion time is minimized. Our CP framework generates optimal implementations and has been evaluated using synthetic as well as real-life case studies.

@inproceedings{Minhass:2012ac,
  author = {Minhass, {Wajid Hassan} and Paul Pop and Jan Madsen},
  title = {Synthesis of Biochemical Applications on Flow-Based Microfluidic Biochips using Constraint Programming},
  booktitle = {Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)},
  publisher = {IEEE},
  year = {2012},
  url = {http://cmp.imag.fr/Conferences/dtip/dtip2012/}
}

In this article, we propose a strategy for the synthesis of fault-tolerant schedules and for the mapping of fault-tolerant applications. Our techniques handle transparency/performance trade-offs and use the faultoccurrence information to reduce the overhead due to fault tolerance. Processes and messages are statically scheduled, and we use process reexecution for recovering from multiple transient faults. We propose a finegrained transparent recovery, where the property of transparency can be selectively applied to processes and messages. Transparency hides the recovery actions in a selected part of the application so that they do not affect the schedule of other processes and messages. While leading to longer schedules, transparent recovery has the advantage of both improved debuggability and less memory needed to store the faulttolerant schedules.

@article{Izosimov:2012aa,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Scheduling and Optimization of Fault-Tolerant Embedded Systems with Transparency/Performance Trade-Offs},
  journal = {ACM Transactions on Embedded Computing Systems},
  publisher = {Association for Computing Machinery, Inc.},
  year = {2012},
  doi = {10.1145/2345770.2345773},
  url = {http://dx.doi.org/10.1145/2345770.2345773}
}

Distributed Real-time Embedded (DRE) systems are facing great challenges in networked, unpredictable and especially unsecured environments. In such systems, there is a strong need to enforce security on distributed computing nodes in order to guard against potential threats, while satisfying the real-time requirements. This paper proposes a Security-Aware Feedback Control Mechanism (SAFCM) which has the ability to dynamically change the security level to guarantee soft real-time requirements and make the security protection as strong as possible. In order to widely support distributed real-time systems, a multi-input multi-output feedback loop is designed and a model predictive controller is deployed based on an equation model that describes the dynamic behavior of the DRE systems. This control loop uses security level scaling to globally control the CPU utilization and security performance for the whole system. We propose a "security level" metric based on an evolution of cryptography algorithms used in embedded systems. Experimental results demonstrate that SAFCM not only has the excellent adaptivity compared to open-loop mechanism, but also has a better overall performance than PID control mechanism.

@inproceedings{Ma:2012aa,
  author = {Yue Ma and Wei Jiang and Nan Sang and Paul Pop},
  title = {SAFCM: A Security-Aware Feedback Control Mechanism for Distributed Real-Time Embedded Systems},
  booktitle = {International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)},
  publisher = {IEEE},
  year = {2012},
  doi = {10.1109/RTCSA.2012.31},
  url = {http://dx.doi.org/10.1109/RTCSA.2012.31}
}

Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis. The “digital” biochips are manipulating liquids as discrete droplets on a two-dimensional array of electrodes. Basic microfluidic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a series of electrodes. So far, researchers have assumed that these operations are executed on virtual rectangular devices, formed by grouping several adjacent electrodes. One drawback is that all electrodes are considered occupied during the operation execution, although the droplet uses only one electrode at a time. Moreover, the operations can actually be performed by routing the droplets on any sequence of electrodes on the microfluidic array. Hence, in this paper, we eliminate the concept of virtual devices and allow the droplets to move on the chip on any route during operation execution. Thus, the synthesis problem is transformed into a routing problem. We develop an algorithm based on a Greedy Randomized Adaptive Search Procedure (GRASP) and we show that routing-based synthesis leads to significant improvements in the application completion time compared to traditional synthesis based on virtual devices. However, the disadvantage of the routing-based approach is that it may contaminate larger areas of the biochip, when synthesizing applications containing liquids which may adsorb on the surface of the microfluidic array. We have extended the GRASP-based algorithm to consider contamination avoidance during routing-based synthesis. Several real-life examples and synthetic benchmarks are used to evaluate the proposed approaches.

@article{Maftei:2012aa,
  author = {Elena Maftei and Paul Pop and Jan Madsen},
  title = {Routing-based Synthesis of Digital Microfluidic Biochips},
  journal = {Design Automation for Embedded Systems},
  publisher = {Springer New York LLC},
  year = {2012},
  doi = {10.1007/s10617-012-9083-0},
  url = {http://dx.doi.org/10.1007/s10617-012-9083-0}
}

We are interested in mapping hard real-time applications on distributed heterogeneous architectures. An application is modeled as a set of tasks, and we consider a fixed-priority preemptive scheduling policy. We target the early design phases, when decisions have a high impact on the subsequent implementation choices. However, due to a lack of information, the early design phases are characterized by uncertainties, e.g., in the worst-case execution times (wcets), or in the functionality requirements. We model uncertainties in the wcets using the “percentile method”. The uncertainties in the functionality requirements are captured using “future scenarios”, which are task sets that model functionality likely to be added in the future. In this context, we derive a mapping of tasks in the application, such that the resulted implementation is both robust and flexible. Robust means that the application has a high chance of being schedulable, considering the wcet uncertainties, whereas a flexible mapping has a high chance to successfully accommodate the future scenarios. We propose a Genetic Algorithm-based approach to solve this optimization problem. Extensive experiments show the importance of taking into account the uncertainties during the early design phases.

@inproceedings{Gan:2012aa,
  author = {Junhe Gan and Paul Pop and Flavius Gruian and Jan Madsen},
  title = {Robust and flexible mapping for real-time distributed applications during the early design phases},
  booktitle = {Conference on Design, Automation and Test in Europe},
  publisher = {Association for Computing Machinery},
  year = {2012},
  url = {http://www.date-conference.com/}
}

Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis using microfluidics. The digital microfluidic biochips are based on the manipulation of liquids not as a continuous flow, but as discrete droplets. Researchers have presented approaches for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determine the allocation, resource binding, scheduling, placement and routing of the operations in the application. The droplet volumes can vary erroneously due to parametric faults, thus impacting negatively the correctness of the application. Researchers have proposed approaches that synthesize offline predetermined recovery subroutines, which are activated online when errors occur. In this paper, we propose an online synthesis strategy, which determines the appropriate recovery actions at the moment when faults are detected. We have also proposed a biochemical application model which can capture both time-redundant and space-redundant recovery operations. Experiments performed on three real-life case studies show that, by taking into account the biochip configuration when errors occur, our online synthesis is able to reduce the application times.

@inproceedings{Alistar:2012aa,
  author = {Mirela Alistar and Paul Pop and Jan Madsen},
  title = {Online Synthesis for Error Recovery in Digital Microfluidic Biochips with Operation Variability},
  booktitle = {Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)},
  publisher = {IEEE},
  year = {2012},
  url = {http://cmp.imag.fr/Conferences/dtip/dtip2012/}
}

Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the basic functions for biochemical analysis. On a “digital” biochip liquids are manipulated as discrete droplets on a two-dimensional microfluidic array of electrodes. Basic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a group of electrodes, forming a virtual device. Initially researchers have ignored the locations of droplets during operation execution, and have considered that all electrodes inside devices are occupied.We have recently proposed a droplet-aware approach for the execution of operations on the microfluidic array, in which the locations of droplets inside devices are known at each time step. In this article we extend the droplet-aware approach to consider the synthesis of biochips which contain defective electrodes on the microfluidic array. We show that for such biochips knowing the exact locations of droplets during operation execution leads to significant improvements in the completion time of applications.

@inproceedings{Maftei:2012ab,
  author = {Elena Maftei and Paul Pop and Jan Madsen},
  title = {Droplet-Aware Module-Based Synthesis for Fault-Tolerant Digital Microfluidic Biochips},
  booktitle = {Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)},
  publisher = {IEEE},
  year = {2012},
  url = {http://cmp.imag.fr/Conferences/dtip/dtip2012/}
}

This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It presents an over-view of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program. The paper briefly presents the results of our analysis of the main problems to be solved and challenges to be faced in the design of such heterogeneous MPSoCs. It explains which system, design, and electronic design automation (EDA) concepts seem to be adequate to resolve the problems and address the challenges. Finally, it introduces and briefly discusses the ASAM design-flow and its main stages.

@inproceedings{Jozwiak:2012aa,
  author = {L. Jozwiak and M. Lindwer and R. Corvino and P. Meloni and Laura Micconi and Jan Madsen and E. Diken and Deepak Gangadharan and R. Jordans and S. Pomata and Paul Pop and G. Tuveri and L. Raffo},
  title = {ASAM: Automatic Architecture Synthesis and Application Mapping},
  booktitle = {Euromicro Conference on Digital System Design},
  publisher = {IEEE},
  year = {2012},
  doi = {10.1109/DSD.2012.28},
  url = {http://dx.doi.org/10.1109/DSD.2012.28}
}

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. In this paper we are interested in flow-based biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. The manufacturing technology, soft lithography, used for the flow-based biochips is advancing faster than Moore's law, resulting in increased architectural complexity. However, the designers are still using full-custom and bottom-up, manual techniques in order to design and implement these chips. As the chips become larger and the applications become more complex, the manual methodologies will not scale, becoming highly inadequate. Therefore, for the first time to our knowledge,we propose a top-down architectural synthesis methodology for the flow-based biochips. Starting from a given biochemical application and a microfluidic component library, we are interested in synthesizing a biochip architecture, i.e., performing component allocation from the library based on the biochemical application, generating the biochip schematic (netlist) and then performing physical synthesis (deciding the placement of the microfluidic components on the chip and performing routing of the microfluidic channels), such that the application completion time is minimized. We evaluate our proposed approach by synthesizing architectures for real-life applications as well as synthetic benchmarks.

@inproceedings{Minhass:2012ab,
  author = {Minhass, {Wajid Hassan} and Paul Pop and Jan Madsen and Blaga, {Felician Stefan}},
  title = {Architectural Synthesis of Flow-Based Microfluidic Large-Scale Integration Biochips},
  booktitle = {International Conference on Compilers, Architecture and Synthesis for Embedded Systems},
  publisher = {Association for Computing Machinery},
  year = {2012},
  doi = {10.1145/2380403.2380437},
  url = {http://dx.doi.org/10.1145/2380403.2380437}
}

In this paper we are interested in mixed-criticality applications implemented using distributed heterogenous architectures, composed of processing elements (PEs) interconnected using the TTEthernet protocol. At the PE-level, we use partitioning, such that each application is allowed to run only within predefined time slots, allocated on each processor. At the communication-level, TTEthernet uses the concepts of virtual links for the separation of mixed-criticality messages. TTEthernet integrates three types of traffic: Time-Triggered (TT) messages, transmitted based on schedule tables, Rate Constrained (RC) messages, transmitted if there are no TT messages, and Best Effort (BE) messages. We assume that applications are scheduled using Static Cyclic Scheduling (SCS) or Fixed-Priority Preemptive Scheduling (FPS). We are interested in analysis and optimization methods and tools, which decide the mapping of tasks to PEs, the sequence and length of the time partitions on each PE and the schedule tables of the SCS tasks and TT messages, such that the applications are schedulable and the response times of FPS tasks and RC messages is minimized. We have proposed a Tabu Search-based meta-heuristic to solve this optimization problem, which has been evaluated using several benchmarks.

@inproceedings{Tamas-Selicean:2012aa,
  author = {Domitian Tamas-Selicean and Sorin Ovidiu Marinescu and Paul Pop},
  title = {Analysis and Optimization of Mixed-Criticality Applications on Partitioned Distributed Architectures},
  booktitle = {IET System Safety Conference},
  publisher = {Institution of Engineering and Technology},
  year = {2012},
  doi = {10.1049/cp.2012.1504},
  url = {http://dx.doi.org/10.1049/cp.2012.1504}
}

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. There are several types of microfluidic biochips, each having its advantages and limitations. In this paper we are interested in flow-based biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. Although researchers have proposed significant work on the system-level synthesis of droplet-based biochips, which manipulate droplets on a two-dimensional array of electrodes, no research on system-level synthesis of flow-based biochips has been reported so far. The focus has been on application modeling and component-level simulation. Therefore, for the first time to our knowledge, we propose a system-level modeling and synthesis approach for flow-based biochips. We have developed a topology graph-based model of the biochip architecture, and we have used a sequencing graph to model the biochemical applications. We consider that the architecture of the biochip is given, and we are interested to synthesize an implementation, consisting of the binding of operations in the application to the functional units of the architecture, the scheduling of operations and the routing and scheduling of the fluid flows, such that the application completion time is minimized. We propose a List Scheduling-based heuristic for solving this problem. The proposed heuristic has been evaluated using two real-life case studies and a set of four synthetic benchmarks.

@inproceedings{Minhass:2011ab,
  author = {Minhass, {Wajid Hassan} and Paul Pop and Jan Madsen},
  title = {System-Level Modeling and Synthesis of Flow-Based Microfluidic Biochips},
  booktitle = {International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)},
  publisher = {IEEE},
  year = {2011},
  doi = {10.1145/2038698.2038733},
  url = {http://dx.doi.org/10.1145/2038698.2038733}
}

@inbook{Izosimov:2011aa,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Synthesis of Flexible Fault-Tolerant Schedules for Embedded Systems with Soft and Hard Timing Constraints},
  booktitle = {Design and Test Technology for Dependable Systems-on-Chip},
  publisher = {IGI Global},
  year = {2011}
}

@inproceedings{Pop:2011ab,
  author = {Paul Pop and Elena Maftei and Jan Madsen},
  title = {Recent Research and Emerging Challenges in the System-Level Design of Digital Microfluidic Biochips},
  booktitle = {International SoC Conference},
  publisher = {IEEE},
  year = {2011},
  doi = {10.1109/SOCC.2011.6085142},
  url = {http://dx.doi.org/10.1109/SOCC.2011.6085142}
}

In this paper we are interested in mixed-criticality embedded real-time applications mapped on distributed heterogeneous architectures. The architecture provides both spatial and temporal partitioning, thus enforcing enough separation for the critical applications. With temporal partitioning, each application is allowed to run only within predefined time slots, allocated on each processor. The sequence of time slots for all the applications on a processor are grouped within a Major Frame, which is repeated periodically. We assume that the safety-critical applications (on all criticality levels) are scheduled using static-cyclic scheduling and the noncritical applications are scheduled using fixed-priority preemptive scheduling. We consider that each application runs in a separate partition, and each partition is allocated several time slots on the processors where the application is mapped. We are interested to determine the sequence and size of the time slots within the Major Frame on each processor such that both the safety-critical and non-critical applications are schedulable. We have proposed a Simulated Annealing-based approach to solve this optimization problem. The proposed algorithm has been evaluated using several synthetic and real-life benchmarks.

@inproceedings{Tamas-Selicean:2011ab,
  author = {Domitian Tamas-Selicean and Paul Pop},
  title = {Optimization of Time-Partitions for Mixed-Criticality Real-Time Distributed Embedded Systems},
  booktitle = {International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops},
  publisher = {IEEE},
  year = {2011},
  doi = {10.1109/ISORCW.2011.11},
  url = {http://dx.doi.org/10.1109/ISORCW.2011.11}
}

This paper presents an approach to the synthesis of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Our synthesis approach decides the mapping of tasks to processing elements, as well as the voltage and frequency levels for executing each task, such that transient faults are tolerated, the timing constraints of the application are satisfied, and the energy consumed is minimized. Tasks are scheduled using fixed-priority preemptive scheduling, while replication is used for recovery from multiple transient faults. Addressing energy and reliability simultaneously is especially challenging, since lowering the voltage to reduce the energy consumption has been shown to increase the transient fault rate. We presented a Tabu Search-based approach which uses an energy/reliability trade-off model to find reliable and schedulable implementations with limited energy and hardware resources. We evaluated the algorithm proposed using several synthetic and reallife benchmarks.

@inproceedings{Gan:2011aa,
  author = {Junhe Gan and Flavius Gruian and Paul Pop and Jan Madsen},
  title = {Energy/Reliability Trade-offs in Fault-Tolerant Event-Triggered Distributed Embedded Systems},
  booktitle = {Asia and South Pacific Design Automation Conference (ASP-DAC)},
  publisher = {IEEE},
  year = {2011},
  doi = {10.1109/ASPDAC.2011.5722283},
  url = {http://dx.doi.org/10.1109/ASPDAC.2011.5722283}
}

Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the basic functions for biochemical analysis. The “digital” microfluidic biochips (DMFBs) are manipulating liquids not as a continuous flow, but as discrete droplets on a two-dimensional array of electrodes. Basic microfluidic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a series of electrodes. The challenges facing biochips are similar to those faced by microelectronics some decades ago. To meet the challenges of increasing design complexity, computer-aided-design (CAD) tools are being developed for DMFBs. This paper provides an overview of DMFBs and describes emerging CAD tools for the automated synthesis and optimization of DMFB designs, from fluidic-level synthesis and chip-level design to testing. Design automations are expected to alleviate the burden of manual optimization of bioassays, time-consuming chip designs, and costly testing and maintenance procedures. With the assistance of CAD tools, users can concentrate on the development and abstraction of nanoscale bioassays while leaving chip optimization and implementation details to CAD tools.

@inproceedings{Ho:2011aa,
  author = {Tsung-Yi Ho and Krishnendu Chakrabarty and Paul Pop},
  title = {Digital Microfluidic Biochips: Recent Research and Emerging Challenges},
  booktitle = {International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)},
  publisher = {IEEE},
  year = {2011},
  doi = {10.1145/2039370.2039422},
  url = {http://dx.doi.org/10.1145/2039370.2039422}
}

@inbook{Pop:2011aa,
  author = {Paul Pop and Alois Goller and Traian Pop and Petru Eles},
  title = {Development Tools},
  booktitle = {Time-Triggered Communication},
  publisher = {CRC Press},
  year = {2011}
}

In this paper we are interested to implement mixed-criticality hard real-time applications on a given heterogeneous distributed architecture. Applications have different criticality levels, captured by their Safety-Integrity Level (SIL), and are scheduled using static-cyclic scheduling. Mixed-criticality tasks can be integrated onto the same architecture only if there is enough spatial and temporal separation among them. We consider that the separation is provided by partitioning, such that applications run in separate partitions, and each partition is allocated several time slots on a processor. Tasks of different SILs can share a partition only if they are all elevated to the highest SIL among them. Such elevation leads to increased development costs.We are interested to determine (i) the mapping of tasks to processors, (ii) the assignment of tasks to partitions, (iii) the sequence and size of the time slots on each processor and (iv) the schedule tables, such that all the applications are schedulable and the development costs are minimized. We have proposed a Tabu Search-based approach to solve this optimization problem. The proposed algorithm has been evaluated using several synthetic and real-life benchmarks.

@inproceedings{Tamas-Selicean:2011aa,
  author = {Domitian Tamas-Selicean and Paul Pop},
  title = {Design Optimization of Mixed-Criticality Real-Time Applications on Cost-Constrained Partitioned Architectures},
  booktitle = {Real-Time Systems Symposium},
  publisher = {IEEE},
  year = {2011},
  doi = {10.1109/RTSS.2011.11},
  url = {http://dx.doi.org/10.1109/RTSS.2011.11}
}

Microfluidic biochips offer a promising alternative to a conventional biochemical laboratory, integrating all necessary functionalities on-chip in order to perform biochemical applications. Researchers have started to propose computer-aided design tools for the synthesis of such biochips. Our focus in this paper is on the optimization of how a biochemical application is performed on a biochip. In this paper, we consider cell culture biochips, where several cell colonies are exposed to soluble compounds and monitored in real-time to determine the right combination of factors that leads to the desired results. These biochips have high research potential, e.g., cancer research, stem cell, drug discovery. The application considered is a full-factorial experimental design, where all possible combinations of compounds are applied. We are interested to automatically synthesize (currently done manually) the settings of an experimental design, consisting of decision on the placement pattern of cell colonies and the insertion schedule of compounds such that the biochip throughput is maximized, thus increasing the system productivity, saving time and reducing costs. We have proposed a Simulated Annealing metaheuristic for experimental design generation for the cell culture microfluidic biochips, and we have evaluated our approach using multiple experimental setups.

@inproceedings{Minhass:2011aa,
  author = {Minhass, {Wajid Hassan} and Paul Pop and Jan Madsen and Mette Hemmingsen and Peder Skafte-Pedersen and Martin Dufva},
  title = {Cell Culture Microfluidic Biochips: Experimental Throughput Maximization},
  booktitle = {International Conference on Bioinformatics and Biomedical Engineering},
  publisher = {IEEE},
  year = {2011},
  doi = {10.1109/icbbe.2011.5779991},
  url = {http://dx.doi.org/10.1109/icbbe.2011.5779991}
}

In this paper we are interested in the mapping of embedded applications on a dynamically reconfigurable self-healing hardware architecture known as the eDNA (electronic DNA) architecture. The architecture consists of an array of cells interconnected through a 2D-mesh topology. Each cell consists of a processor and an Arithmetic Logic Unit (ALU). Applications are modeled as task graphs. We propose a Tabu Search-based approach for the mapping of an application to the reconfigurable architecture, such that the performance is maximized. When faults occur, the self-healing moves the affected functionality to spare-cells. We optimize the number and placement of spare-cells such that the performance overhead is minimized in the fault-free scenario and the application degrades gracefully in case of faults. This has been done using three different spare-cell placement strategies. We use Monte Carlo simulation to determine the average performance overhead increase due to fault occurrences. The approach has been evaluated using a large number of benchmarks and have shown that the performance loss is reduced with 16% for the best spare-cell placement strategy.

@inproceedings{Boesen:2011ab,
  author = {Boesen, {Michael Reibel} and Jan Madsen and Paul Pop},
  title = {Application-Aware Optimization of Redundant Resources for the Reconfigurable Self-Healing eDNA Hardware Architecture},
  booktitle = {NASA/ESA Conference on Adaptive Hardware and Systems},
  publisher = {IEEE},
  year = {2011},
  doi = {10.1109/AHS.2011.5963918},
  url = {http://dx.doi.org/10.1109/AHS.2011.5963918}
}

In this paper we are interested in mixed hard/soft real-time fault-tolerant applications mapped on distributed heterogeneous architectures. We use the Earliest Deadline First (EDF) scheduling for the hard real-time tasks and the Constant Bandwidth Server (CBS) for the soft tasks. The bandwidth reserved for the servers determines the quality of service (QoS) for soft tasks. CBS enforces temporal isolation, such that soft task overruns do not affect the timing guarantees of hard tasks. Transient faults in hard tasks are tolerated using checkpointing with rollback recovery. We have proposed a Tabu Search-based approach for task mapping and CBS bandwidth reservation, such that the deadlines for the hard tasks are satisfied, even in the case of transient faults, and the QoS for the soft tasks is maximized. Researchers have used fixed execution time models, such as the worst-case execution times for hard tasks and average execution times for soft tasks. However, we show that by using stochastic execution times for soft tasks, significant improvements can be obtained. The proposed strategy has been evaluated using an extensive set of benchmarks.

@inproceedings{Saraswat:2010aa,
  author = {Saraswat, {Prabhat Kumar} and Paul Pop and Jan Madsen},
  title = {Task Mapping and Bandwidth Reservation for Mixed Hard/Soft Fault-Tolerant Embedded Systems},
  booktitle = {IEEE Symposium on Real-Time and Embedded Technology and Applications},
  publisher = {IEEE},
  year = {2010},
  doi = {10.1109/RTAS.2010.31},
  url = {http://dx.doi.org/10.1109/RTAS.2010.31}
}

Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis. The "digital" microfluidic biochips are manipulating liquids not as a continuous flow, but as discrete droplets, and hence they are highly reconfigurable and scalable. A digital biochip is composed of a two-dimensional array of cells, together with reservoirs for storing the samples and reagents. Several adjacent cells are dynamically grouped to form a virtual device, on which operations are performed. So far, researchers have assumed that throughout its execution, an operation is performed on a rectangular virtual device, whose position remains fixed. However, during the execution of an operation, the virtual device can be reconfigured to occupy a different group of cells on the array, forming any shape, not necessarily rectangular. In this paper, we present a Tabu Search metaheuristic for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determines the allocation, resource binding, scheduling and placement of the operations in the application. In our approach, we consider changing the device to which an operation is bound during its execution, to improve the completion time of the biochemical application. Moreover, we devise an analytical method for determining the completion time of an operation on a device of any given shape. The proposed heuristic has been evaluated using a real-life case study and ten synthetic benchmarks.

@article{Maftei:2010aa,
  author = {Elena Maftei and Paul Pop and Jan Madsen},
  title = {Tabu Search-based Synthesis of Digital Microfluidic Biochips with Dynamically Reconfigurable Non-rectangular Devices},
  journal = {Design Automation for Embedded Systems},
  publisher = {Springer},
  year = {2010},
  doi = {10.1007/s10617-010-9059-x},
  url = {http://dx.doi.org/10.1007/s10617-010-9059-x}
}

Microfluidic biochips offer a promising alternative to a conventional biochemical laboratory. There are two technologies for the microfluidic biochips: droplet-based and flow-based. In this paper we are interested in flow-based microfluidic biochips, where the liquid flows continuously through pre-defined micro-channels using valves and pumps. We present an approach to the system-level modeling and simulation of a cell culture microfluidic biochip called ProCell, Programmable Cell Culture Chip. ProCell contains a cell culture chamber, which is envisioned to run 256 simultaneous experiments (viewed as a 16 × 16 matrix). We use an inverted fluorescence microscope to observe the experiments in real-time, allowing kinetic data analysis. We are able to automatically adjust the current experimental setup thus allowing, for the first time, conditional experiments. We propose a biochip architecture model and a comprehensive fault model that captures permanent faults occurring during chip operation. Using the proposed modeling and simulation framework, we perform an architectural level evaluation of two cell culture chamber implementations. A qualitative success metric is also proposed to evaluate chip performance in the presence of partial failures. Our results show that significant improvements in efficiency can be obtained using redundancy, providing improved chances to complete an experiment even in the presence of faults. This decreases the experiment repetition rate while increasing system productivity, saving time and reducing costs.

@inproceedings{Minhass:2010ab,
  author = {Minhass, {Wajid Hassan} and Paul Pop and Jan Madsen and Mette Hemmingsen and Martin Dufva},
  title = {System-level modeling and simulation of the cell culture microfluidic biochip ProCell},
  booktitle = {Symposium on Design Test Integration and Packaging of MEMS/MOEMS},
  publisher = {IEEE},
  year = {2010},
  url = {http://www.ieee.org/conferences\_events/conferences/conferencedetails/index.html?Conf\_ID=16860}
}

Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis using microfluidics. The digital microfluidic biochips are based on the manipulation of liquids not as a continuous flow, but as discrete droplets. Researchers have presented approaches for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determine the allocation, resource binding, scheduling and placement of the operations in the application. Existing approaches consider that on-chip operations, such as splitting a droplet of liquid, are perfect. However, these operations have variability margins, which can impact the correctness of the biochemical application.We consider that a split operation, which goes beyond specified variability bounds, is faulty. The fault is detected using on-chip volume sensors. We have proposed an abstract model for a biochemical application, consisting of a sequencing graph, which can capture all the fault scenarios in the application. Starting from this model, we have proposed a synthesis approach that, for a given chip area and number of sensors, can derive a fault-tolerant implementation. Two fault-tolerant scheduling techniques have been proposed and compared. We show that, by taking into account fault-occurrence information, we can derive better quality implementations, which leads to shorter application completion times, even in the case of faults. The proposed synthesis approach under operation variability has been evaluated using several benchmarks.

@inproceedings{Alistar:2010aa,
  author = {Mirela Alistar and Elena Maftei and Paul Pop and Jan Madsen},
  title = {Synthesis of biochemical applications on digital microfluidic biochips with operation variability},
  booktitle = {Symposium on Design Test Integration and Packaging of MEMS/MOEMS},
  publisher = {IEEE},
  year = {2010},
  url = {http://www.ieee.org/conferences\_events/conferences/conferencedetails/index.html?Conf\_ID=16860}
}

@inproceedings{Minhass:2010aa,
  author = {Minhass, {Wajid Hassan} and Paul Pop and Jan Madsen},
  title = {Simulation-Based Evaluation of Redundancy Schemes for a Cell Culture Microfluidic Biochip},
  booktitle = {Proceedings of the 4th Nordic Workshop on Dependability and Security},
  year = {2010}
}

Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the basic functsions for biochemical analysis. The "digital" microfluidic biochips are manipulating liquids not as a continuous flow, but as discrete droplets on a two-dimensional array of electrodes. Basic microfluidic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a series of electrodes. So far, researchers have assumed that these operations are executed on rectangular virtual devices, formed by grouping several adjacent electrodes. One drawback is that all electrodes are considered occupied during the operation execution, although the droplet uses only one electrode at a time. Moreover, the operations can actually execute by routing the droplets on any sequence of electrodes on the array. Hence, in this paper, we eliminate the concept of virtual modules and allow the droplets to move on the chip on any route during operation execution. Thus, the synthesis problem is transformed into a routing problem. We propose an approach derived from a Greedy Randomized Adaptive Search Procedure (GRASP) and we show that by considering routing-based synthesis, significant improvements can be obtained in the application completion time. The proposed heuristic has been evaluated using two real-life case studies and ten synthetic benchmarks.

@inproceedings{Maftei:2010ab,
  author = {Elena Maftei and Paul Pop and Jan Madsen},
  title = {Routing-based Synthesis of Digital Microfluidic Biochips},
  booktitle = {International Conference on Compilers, Architectures and Synthesis for Embedded Systems},
  year = {2010},
  doi = {10.1145/1878921.1878928},
  url = {http://dx.doi.org/10.1145/1878921.1878928}
}

In this paper we are interested in mixed-criticality embedded applications implemented on distributed architectures. Depending on their time-criticality, tasks can be hard or soft real-time and regarding safety-criticality, tasks can be fault-tolerant to transient faults, permanent faults, or have no dependability requirements. We use Earliest Deadline First (EDF) scheduling for the hard tasks and the Constant Bandwidth Server (CBS) for the soft tasks. The CBS parameters determine the quality of service (QoS) of soft tasks. Transient faults are tolerated using checkpointing with roll- back recovery. For tolerating permanent faults in processors, we use task migration, i.e., restarting the safety-critical tasks on other processors. We propose a Greedy-based on- line heuristic for the migration of safety-critical tasks, in response to permanent faults, and the adjustment of CBS parameters on the target processors, such that the faults are tolerated, the deadlines for the hard real-time tasks are satisfied and the QoS for soft tasks is maximized. The proposed online adaptive approach has been evaluated using several synthetic benchmarks and a real-life case study.

@article{Saraswat:2009aa,
  author = {Saraswat, {Prabhat Kumar} and Paul Pop and Jan Madsen},
  title = {Task Migration for Fault-Tolerance in Mixed-Criticality Embedded Systems},
  journal = {SIGBED Review--Special Issue on the International Workshop on Adaptive and Reconfigurable Embedded Systems},
  booktitle = {SIGBED Review--Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES'09)},
  year = {2009},
  doi = {10.1145/1851340.1851348},
  url = {https://doi.org/10.1145/1851340.1851348}
}

@inproceedings{Maftei:2009aa,
  author = {Elena Maftei and Paul Pop and Jan Madsen},
  title = {Tabu Search-Based Synthesis of Dynamically Reconfigurable Digital Microfluidic Biochips},
  booktitle = {International Conference on Compilers, Architecture and Synthesis for Embedded Systems},
  year = {2009},
  doi = {10.1145/1629395.1629423},
  url = {http://dx.doi.org/10.1145/1629395.1629423}
}

We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes and communications are statically scheduled. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that multiple transient faults are tolerated and the timing constraints of the application are satisfied. We present several design optimization approaches which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

@article{Pop:2009aa,
  author = {Paul Pop and Viacheslav Izosimov and Petru Eles and Zebo Peng},
  title = {Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems with Checkpointing and Replication},
  journal = {IEEE Transactions on Very Large Scale Integration Systems},
  publisher = {Institute of Electrical and Electronics Engineers Inc.},
  year = {2009},
  doi = {10.1109/TVLSI.2008.2003166},
  url = {http://dx.doi.org/10.1109/TVLSI.2008.2003166}
}

In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process reexecution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of reexecutions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.

@inproceedings{Izosimov:2009aa,
  author = {Viacheslav Izosimov and Ilia Polian and Paul Pop},
  title = {Analysis and Optimization of Fault-tolerant Embedded Systems with Hardened Processors},
  booktitle = {Conference on Design, Automation and Test in Europe},
  publisher = {European Design and Automation Association},
  year = {2009}
}

@article{Pop:2008ab,
  author = {Pop, Traian and Pop, Paul and Eles, Petru and Peng, Zebo and Andrei, Alexandru},
  title = {Timing analysis of the FlexRay communication protocol},
  journal = {Real-time systems},
  year = {2008},
  doi = {10.1007/s11241-007-9040-3},
  url = {https://doi.org/10.1007/s11241-007-9040-3}
}

@inproceedings{Maftei:2008ab,
  author = {Elena Maftei and Paul Pop and {Popentiu Vladicescu}, Florin},
  title = {Synthesis of Reliable Digital Microfluidic Biochips using Monte Carlo Simulation},
  booktitle = {Conference of the European Safety and Reliability Association},
  year = {2008}
}

In this paper we present an approach for scheduling with preemption for fault-tolerant embedded systems composed of soft and hard real-time processes. We are interested to maximize the overall utility for average, most likely to happen, scenarios and to guarantee the deadlines for the hard processes in the worst case scenarios. In many applications, the worst-case execution times of processes can be much longer than their average execution times. Thus, designs for the worst-case can be overly pessimistic, i.e., result in low overall utility. We propose preemption of process executions as a method to generate flexible schedules that maximize the overall utility for the average case while guarantee timing constraints in the worst case. Our scheduling algorithms determine off-line when to preempt and when to resurrect processes. The experimental results show the superiority of our new scheduling approach compared to approaches without preemption.

@inproceedings{Izosimov:2008ab,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems},
  booktitle = {Euromicro Conference on Digital System Design},
  publisher = {IEEE},
  year = {2008},
  doi = {10.1109/DSD.2008.47},
  url = {http://dx.doi.org/10.1109/DSD.2008.47}
}

This work addresses the issue of design optimization for fault- tolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpointing with rollback recovery and active replication. Fault tolerant schedules are generated based on a conditional process graph representation. The formulated system synthesis approaches decide the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors, such that multiple transient faults are tolerated, transparency requirements are considered, and the timing constraints of the application are satisfied.

@inproceedings{Eles:2008aa,
  author = {Petru Eles and Viacheslav Izosimov and Paul Pop and Zebo Peng},
  title = {Synthesis of Fault-Tolerant Embedded Systems},
  booktitle = {Conference on Design, Automation, and Test in Europe},
  year = {2008},
  doi = {10.1109/DATE.2008.4484825},
  url = {http://dx.doi.org/10.1109/DATE.2008.4484825}
}

In this paper we present an approach to the synthesis of fault-tolerant schedules for embedded applications with soft and hard real-time constraints. We are interested to guarantee the deadlines for the hard processes even in the case of faults, while maximizing the overall utility. We use time/utility functions to capture the utility of soft processes. Process re-execution is employed to recover from multiple faults. A single static schedule computed off-line is not fault tolerant and is pessimistic in terms of utility, while a purely online approach, which computes a new schedule every time a process fails or completes, incurs an unacceptable overhead. Thus, we use a quasi-static scheduling strategy, where a set of schedules is synthesized off-line and, at run time, the scheduler will select the right schedule based on the occurrence of faults and the actual execution times of processes. The proposed schedule synthesis heuristics have been evaluated using extensive experiments.

@inproceedings{Izosimov:2008aa,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints},
  booktitle = {Conference on Design, Automation and Test in Europe},
  year = {2008},
  doi = {10.1109/DATE.2008.4484791},
  url = {http://dx.doi.org/10.1109/DATE.2008.4484791}
}

@inproceedings{Maftei:2008aa,
  author = {Elena Maftei and Paul Pop and Jan Madsen and Stidsen, {Thomas K.}},
  title = {Placement-Aware Architectural Synthesis of Digital Microfluidic Biochips using ILP},
  booktitle = {International Conference on Very Large Scale Integration},
  publisher = {IEEE},
  year = {2008},
  url = {https://www.springerprofessional.de/en/vlsi-soc-design-methodologies-for-soc-and-sip/3275798}
}

We present an approach to the analysis and optimisation of heterogeneous multiprocessor embedded systems. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. When several scheduling policies share a resource, they are organised in a hierarchy. In this paper, we first develop a holistic scheduling and schedulability analysis that determines the timing properties of a hierarchically scheduled system. Second, we address design problems that are characteristic to such hierarchically scheduled systems: assignment of scheduling policies to tasks, mapping of tasks to hardware components, and the scheduling of the activities. We also present several algorithms for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilisation of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

@article{Pop:2008aa,
  author = {Traian Pop and Paul Pop and Petru Eles and Zebo Peng},
  title = {Analysis and Optimisation of Hierarchically Scheduled Multiprocessor Embedded Systems},
  journal = {International Journal of Parallel Programming},
  publisher = {Springer},
  year = {2008},
  doi = {10.1007/s10766-007-0059-9},
  url = {http://dx.doi.org/10.1007/s10766-007-0059-9}
}

@inproceedings{Pop:2007ac,
  author = {Traian Pop and Paul Pop and Petru Eles and Zebo Peng and Alexandu Andrei},
  title = {Timing Analysis for the FlexRay Communication Protocol},
  booktitle = {Real-Time in Sweden Conference},
  year = {2007 \color{red}\textbf{Best Paper Award}}
}

In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. Addressing simultaneously energy and reliability is especially challenging because lowering the voltage to reduce the energy consumption has been shown to exponentially increase the number of transient faults. In addition, time-redundancy based fault-tolerance techniques such as re-execution and dynamic voltage scaling-based low-power techniques are competing for the slack in the schedules. Our approach decides the voltage levels and start times of processes and the transmission times of messages, such that the transient faults are tolerated, the timing constraints of the application are satisfied and the energy is minimized. We present a constraint logic programming- based approach which is able to find reliable and schedulable implementations within limited energy and hardware resources. The developed algorithms have been evaluated using extensive experiments.

@inproceedings{Pop:2007ab,
  author = {Paul Pop and Poulsen, {K{\aa}re Harbo} and Viacheslav Izosimov and Petru Eles},
  title = {Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems},
  booktitle = {International Conference on Hardware/Software Codesign and System Synthesis},
  publisher = {Association for Computing Machinery},
  year = {2007},
  doi = {10.1145/1289816.1289873},
  url = {http://dx.doi.org/10.1145/1289816.1289873}
}

This paper presents a design optimisation tool for distributed embedded real-time systems that 1) decides mapping, fault-tolerance policy and generates a fault-tolerant schedule, 2) is targeted for hard real-time, 3) has hard reliability goal, 4) generates static schedule for processes and messages, 5) provides fault-tolerance for k transient/soft faults, 6) optimises for minimal energy consumption, while considering impact of lowering voltages on the probability of faults, 7) uses constraint logic programming (CLP) based implementation.

@inproceedings{Poulsen:2007ab,
  author = {Poulsen, {K{\aa}re Harbo} and Paul Pop and Viacheslav Izosimov},
  title = {Energy-Aware Synthesis of Fault-Tolerant Schedules for Real-Time Distributed Embedded Systems},
  booktitle = {Euromicro Conference on Real-Time Systems, Work-In-Progress},
  year = {2007},
  url = {http://retis.sssup.it/ecrts07/}
}

FlexRay will very likely become the de-facto standard for in-vehicle communications. Its main advantage is the combination of high speed static and dynamic transmission of messages. In our previous work we have shown that not only the static but also the dynamic segment can be used for hard-real time communication in a deterministic manner. In this paper, we propose techniques for optimising the FlexRay bus access mechanism of a distributed system, so that the hard real-time deadlines are met for all the tasks and messages in the system. We have evaluated the proposed techniques using extensive experiments.

@inproceedings{Pop:2007aa,
  author = {Traian Pop and Paul Pop and Petru Eles and Zebo Peng},
  title = {Bus Access Optimisation for FlexRay-based Distributed Embedded Systems},
  booktitle = {Conference on Design, Automation and Test in Europe},
  publisher = {IEEE},
  year = {2007},
  doi = {10.1109/DATE.2007.364566},
  url = {http://dx.doi.org/10.1109/DATE.2007.364566}
}

We present a constraint logic programming (CLP) approach for synthesis of fault-tolerant hard real-time applications on distributed heterogeneous architectures. We address time-triggered systems, where processes and messages are statically scheduled based on schedule tables. We use process re-execution for recovering from multiple transient faults. We propose three scheduling approaches, which each present a trade-off between schedule simplicity and performance, (i) full transparency, (ii) slack sharing and (iii) conditional, and provide various degrees of transparency. We have developed a CLP framework that produces the fault-tolerant schedules, guaranteeing schedulability in the presence of transient faults. We show how the framework can be used to tackle design optimization problems.The proposed approach has been evaluated using extensive experiments.

@inproceedings{Poulsen:2007aa,
  author = {Poulsen, {K{\aa}re Harbo} and Paul Pop and Viacheslav Izosimov},
  title = {A Constraint Logic Programming Framework for the Synthesis of Fault-Tolerant Schedules for Distributed Embedded Systems},
  booktitle = {Conference on Emerging Technologies and Factory Automation},
  publisher = {IEEE},
  year = {2007},
  doi = {10.1109/EFTA.2007.4416850},
  url = {http://dx.doi.org/10.1109/EFTA.2007.4416850}
}

FlexRay will very likely become the de-facto standard for in-vehicle communications. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static (ST) and the dynamic (DYN) segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments.

@inproceedings{Pop:2006ae,
  author = {Traian Pop and Paul Pop and Petru Eles and Zebo Peng},
  title = {Timing Analysis of the FlexRay Communication Protocol},
  booktitle = {Euromicro Conference on Real-Time Systems},
  year = {2006},
  doi = {10.1109/ECRTS.2006.31},
  url = {http://dx.doi.org/10.1109/ECRTS.2006.31}
}

In this paper we present an approach to the scheduling of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. If process recovery is performed such that the operation of other processes is not affected, we call it transparent recovery. Although transparent recovery has the advantages of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules, it will introduce delays that can violate the timing constraints of the application. We propose a novel algorithm for the synthesis of fault-tolerant schedules that can handle the transparency/performance trade-offs imposed by the designer, and makes use of the fault-occurrence information to reduce the overhead due to fault tolerance. We model the application as a conditional process graph, where the fault occurrence information is represented as conditional edges and the transparent recovery is captured using synchronization nodes.

@inproceedings{Izosimov:2006ad,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-offs for Distributed Embedded Systems},
  booktitle = {Conference on Design Automation and Test in Europe},
  year = {2006},
  doi = {10.1109/DATE.2006.244067},
  url = {http://dx.doi.org/10.1109/DATE.2006.244067}
}

We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

@inproceedings{Izosimov:2006ac,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication},
  booktitle = {International Workshop on Electronic Design, Test and Applications},
  year = {2006},
  doi = {10.1109/DELTA.2006.83},
  url = {http://dx.doi.org/10.1109/DELTA.2006.83}
}

@inbook{Pop:2006ad,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems},
  booktitle = {ARTES - A network for Real-Time research and graduate Education in Sweden 1997-2006},
  publisher = {The Department of Information Technology, Uppsala},
  year = {2006}
}

@inproceedings{Izosimov:2006ab,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Optimization of Fault-Tolerant Applications on Distributed Embedded Systems},
  booktitle = {Swedish System-on-Chip Conference},
  year = {2006}
}

In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable

@inproceedings{Izosimov:2006aa,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems},
  booktitle = {Euromicro Conference on Digital System Design},
  year = {2006},
  doi = {10.1109/DSD.2006.65},
  url = {http://dx.doi.org/10.1109/DSD.2006.65}
}

We present an approach to design optimization of multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In this paper, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, process mapping, and the optimization of parameters corresponding to the communication protocol. We present several heuristics for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

@inbook{Pop:2006ac,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications},
  booktitle = {ARTES - A network for Real-Time research and graduate Education in Sweden 1997-2006},
  publisher = {The Department of Information Technology, Uppsala},
  year = {2006}
}

An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous not only in terms of hardware and software components, but also in terms of communication protocols and scheduling policies. In this context, the task of designing such systems is becoming increasingly difficult. The success of new adequate design methods depends on the availability of efficient analysis as well as optimization techniques. In this paper, we present both analysis and optimization approaches for such heterogeneous distributed real-time embedded systems. More specifically, we discuss the schedulability analysis of hard real-time systems, highlighting particular aspects related to the heterogeneous and distributed nature of the applications. We also introduce several design optimization problems characteristic to this class of systems: mapping of functionality, the optimization of the access to the communication channel, and the assignment of scheduling policies to processes. Optimization heuristics aiming at producing a schedulable system, with a given amount of resources, are presented.

@article{Pop:2006aa,
  author = {Paul Pop and Petru Eles and Zebo Peng and Traian Pop},
  title = {Analysis and Optimization of Distributed Real-Time Embedded Systems},
  journal = {ACM Transactions on Design Automation of Electronic Systems},
  publisher = {Association for Computing Machinery},
  year = {2006},
  doi = {10.1145/1142980.1142984},
  url = {http://dx.doi.org/10.1145/1142980.1142984}
}

An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous, not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimisation techniques. Analysis and optimisation techniques for heterogeneous real-time embedded systems are presented in the paper. The authors address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. They present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briefly highlight characteristic design optimisation problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimisation heuristics for frame packing aimed at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach.

@inbook{Pop:2006ab,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Analysis and optimisation of heterogeneous real-time embedded systems},
  booktitle = {System On Chip: Next Generation Electronics},
  publisher = {Institution of Engineering and Technology},
  year = {2006}
}

@article{Pop:2005af,
  author = {Pop, Paul and Eles, Petru and Peng, Zebo},
  title = {Schedulability-driven frame packing for multicluster distributed embedded systems},
  journal = {ACM Transactions on Embedded Computing Systems (TECS)},
  publisher = {ACM},
  year = {2005}
}

We present an approach to the analysis and optimization of heterogeneous distributed embedded systems. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. When several scheduling policies share a resource, they are organized in a hierarchy. In this paper, we address design problems that are characteristic to such hierarchically scheduled systems: assignment of scheduling policies to tasks, mapping of tasks to hardware components, and the scheduling of the activities. We present algorithms for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

@inproceedings{Pop:2005ae,
  author = {Traian Pop and Paul Pop and Petru Eles and Zebo Peng},
  title = {Optimization of Hierarchically Scheduled Heterogeneous Embedded Systems},
  booktitle = {International Conference on Embedded and Real-Time Computing Systems and Applications},
  year = {2005},
  doi = {10.1109/RTCSA.2005.67},
  url = {http://dx.doi.org/10.1109/RTCSA.2005.67}
}

Summary form only given. Embedded systems are everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded systems. Over 99% of the microprocessors produced today are used in embedded systems, and recently the number of embedded systems in use has become larger than the number of humans on the planet. The complexity of embedded systems is growing at a very high pace and the constraints in terms of functionality, performance, low energy consumption, reliability, cost and time-to-market are getting tighter. Therefore, the task of designing such systems is becoming increasingly important and difficult at the same time. New automated design optimization techniques are needed, which are able to: successfully manage the complexity of embedded systems, meet the constraints imposed by the application domain, shorten the time-to-market, and reduce development and manufacturing costs. In this paper, the author introduces several embedded systems design problems, and shows how they can be formulated as optimization problems. Solving such challenging design optimization problems are the key to the success of the embedded systems design

@inproceedings{Pop:2005ad,
  author = {Paul Pop},
  title = {Embedded Systems Design: Optimization Challenges},
  booktitle = {International Conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems},
  publisher = {Springer},
  year = {2005}
}

@inbook{Pop:2005ac,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Distributed Embedded Real-Time Systems: Analysis and Exploration},
  booktitle = {Embedded Systems Design: The ARTIST Roadmap for Research and Development},
  publisher = {Springer},
  year = {2005}
}

In this paper we present an approach to the design optimization of fault-tolerant embedded systems for safety-critical applications. Processes are statically scheduled and communications are performed using the time-triggered protocol. We use process re-execution and replication for tolerating transient faults. Our design optimization approach decides the mapping of processes to processors and the assignment of fault-tolerant policies to processes such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several heuristics which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

@inproceedings{Izosimov:2005aa,
  author = {Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng},
  title = {Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems},
  booktitle = {Conference on Design, Automation and Test in Europe},
  year = {2005},
  doi = {10.1109/DATE.2005.116},
  url = {http://dx.doi.org/10.1109/DATE.2005.116}
}

@inbook{Pop:2005ab,
  author = {Paul Pop and Rolf Ernst and Petru Eles and Zebo Peng},
  title = {Automotive Industry},
  booktitle = {Embedded Systems Design: The ARTIST Roadmap for Research and Development},
  publisher = {Springer},
  year = {2005}
}

An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous, not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimisation techniques. Analysis and optimisation techniques for heterogeneous real-time embedded systems are presented in the paper. The authors address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. They present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briefly highlight characteristic design optimisation problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimisation heuristics for frame packing aimed at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach.

@article{Pop:2005aa,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Analysis and Optimisation of Heterogeneous Real-Time Embedded Systems},
  journal = {IEE Proceedings - Computers and Digital Techniques},
  publisher = {Institution of Engineering and Technology},
  year = {2005},
  doi = {10.1049/ip-cdt:20045069},
  url = {http://dx.doi.org/10.1049/ip-cdt:20045069}
}

In this paper we present an approach to mapping and scheduling of distributed embedded systems for hard real-time applications, aiming at a minimization of the system modification cost. We consider an incremental design process that starts from an already existing system running a set of applications. We are interested to implement new functionality such that the timing requirements are fulfilled, and the following two requirements are also satisfied: the already running applications are disturbed as little as possible, and there is a good chance that, later, new functionality can easily be added to the resulted system. Thus, we propose a heuristic which finds the set of already running applications which have to be remapped and rescheduled at the same time with mapping and scheduling the new application, such that the disturbance on the running system (expressed as the total cost implied by the modifications) is minimized. Once this set of applications has been determined, we outline a mapping and scheduling algorithm aimed at fulfilling the requirements stated above. The approaches have been evaluated based on extensive experiments using a large number of generated benchmarks as well as a real-life example.

@article{Pop:2004ab,
  author = {Paul Pop and Petru Eles and Zebo Peng and Traian Pop},
  title = {Scheduling and Mapping in an Incremental Design Methodology for Distributed Real-Time Embedded Systems},
  journal = {IEEE Transactions on VLSI Systems},
  publisher = {Institute of Electrical and Electronics Engineers Inc.},
  year = {2004},
  doi = {10.1109/TVLSI.2004.831467},
  url = {http://dx.doi.org/10.1109/TVLSI.2004.831467}
}

We present an approach to partitioning and mapping for multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have proposed a schedulability analysis for such systems, including a worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Based on this analysis, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, and process mapping. We present a branch and bound algorithm for solving these problems. Our heuristic is able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

@inproceedings{Pop:2004af,
  author = {Paul Pop and Petru Eles and Zebo Peng and Viacheslav Izosimov},
  title = {Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems},
  booktitle = {Euromicro Conference on Real-Time Systems},
  year = {2004},
  doi = {10.1109/EMRTS.2004.1311010},
  url = {http://dx.doi.org/10.1109/EMRTS.2004.1311010}
}

We present an approach to static priority preemptive process scheduling for the synthesis of hard real-time distributed embedded systems where communication plays an important role. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays with four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the synthesis of communication are developed, and the four approaches to message scheduling are compared using extensive experiments.

@article{Pop:2004aa,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Schedulability-Driven Communication Synthesis for Time-Triggered Embedded Systems},
  journal = {Real-Time Systems Journal},
  publisher = {Springer New York LLC},
  year = {2004},
  doi = {10.1023/B:TIME.0000018246.09796.a3}
}

We present an approach to design optimization of multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In this paper, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, process mapping, and the optimization of parameters corresponding to the communication protocol. We present several heuristics for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

@inproceedings{Pop:2004ad,
  author = {Paul Pop and Petru Eles and Zebo Peng and Viacheslav Izosimov and Magnus Hellring and Olof Bridal},
  title = {Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications},
  booktitle = {Conference on Design, Automation and Test in Europe},
  year = {2004}
}

Embedded computer systems are now everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded computers. An important class of embedded computer systems is that of hard real-time systems, which have to fulfill strict timing requirements. As real-time systems become more complex, they are often implemented using distributed heterogeneous architectures. Analysis and Synthesis of Distributed Real-Time Embedded Systems addresses the design of real-time applications implemented using distributed heterogeneous architectures. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Regarding this last aspect, time-driven and event-driven systems, as well as a combination of the two, are considered. Such systems are used in many application areas like automotive electronics, real-time multimedia, avionics, medical equipment, and factory systems. The proposed analysis and synthesis techniques derive optimized implementations that fulfill the imposed design constraints. An important part of the implementation process is the synthesis of the communication infrastructure, which has a significant impact on the overall system performance and cost. Analysis and Synthesis of Distributed Real-Time Embedded Systems considers the mapping and scheduling tasks within an incremental design process. To reduce the time-to-market of products, the design of real-time systems seldom starts from scratch. Typically, designers start from an already existing system, running certain applications, and the design problem is to implement new functionality on top of this system. Supporting such an incremental design process provides a high degree of flexibility, and can result in important reductions of design costs. Analysis and Synthesis of Distributed Real-Time Embedded Systems will be of interest to advanced undergraduates, graduate students, researchers and designers involved in the field of embedded systems.

@book{Pop:2004ac,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Analysis and Synthesis of Distributed Real-Time Embedded Systems},
  publisher = {Kluwer Academic Publishers},
  year = {2004}
}

@misc{Pop:2004ag,
  author = {Paul Pop},
  title = {Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems},
  booktitle = {Second EDAA Ph.D. Forum, Design Automation and Test in Europe Conference},
  year = {2004}
}

We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable. Thus, we have also proposed a schedulability analysis for applications consisting of mixed event-triggered and time-triggered processes and messages, and a worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach.

@article{Pop:2003ag,
  author = {Pop, Paul and Eles, Petru and Peng, Zebo},
  title = {Schedulability-driven Frame Packing for Multi-cluster Distributed Embedded Systems},
  journal = {SIGPLAN Not.},
  publisher = {Association for Computing Machinery},
  year = {2003},
  doi = {10.1145/780731.780748},
  url = {http://doi.acm.org/10.1145/780731.780748}
}

We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

@inproceedings{Pop:2003ae,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems},
  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
  year = {2003},
  doi = {10.1109/DATE.2003.1253606},
  url = {http://dx.doi.org/10.1109/DATE.2003.1253606}
}

An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.

@article{Pop:2003aa,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems},
  journal = {IEE Proceedings - Computers and Digital Techniques},
  publisher = {Institution of Electrical Engineers (IEE)},
  year = {2003},
  doi = {10.1049/ip-cdt:20030829},
  url = {http://dx.doi.org/10.1049/ip-cdt:20030829}
}

@inproceedings{Pop:2003ac,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Incremental Mapping and Scheduling for Distributed Heterogeneous Real-Time Systems},
  booktitle = {Real-Time in Sweden},
  year = {2003}
}

@misc{Pop:2002ac,
  author = {Paul Pop},
  title = {Scheduling, Mapping and Communication Synthesis for Distributed Real-Time Systems},
  booktitle = {ACM SIGDA PhD Forum at the Design Automation Conference},
  year = {2002}
}

In this paper we present an approach to mapping and scheduling of distributed hard real-time systems, aiming at improving the flexibility of the design process. We consider an incremental design process that starts from an already existing system running a set of applications, with preemptive priority based scheduling at the process level, and time triggered static scheduling at the communication level. We are interested to implement new functionality so that the already running applications are disturbed as little as possible and there is a good chance that, later, new functionality can easily be added to the resulted system. The mapping and scheduling problems are considered in the context of a realistic communication model based on a TDMA protocol. Extensive experiments as well as a real life example demonstrate the relevance of this problem and the efficiency of our solutions.

@inproceedings{Pop:2002ab,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Flexibility Driven Scheduling and Mapping for Distributed Real-Time Systems},
  booktitle = {International Conference on Real-Time Computing Systems and Applications},
  publisher = {I E E E},
  year = {2002}
}

In recent years, many desktop applications have been ported to the world wide web in order to reduce (multiplatform) development, distribution and maintenance costs. However, there is little data concerning the usability of web applications, and the impact of their usability on the total cost of developing and using such applications. In this paper we present a comparison of web and desktop applications from the usability point of view. The comparison is based on an empirical study that investigates the performance of a group of users on two calendaring applications: Yahoo!Calendar and Microsoft Calendar. The study shows that in the case of web applications the performance of the users is significantly reduced, mainly because of the restricted interaction mechanisms provided by current web browsers.

@book{Pop:2002aa,
  author = {Paul Pop},
  title = {Comparing Web Applications with Desktop Applications: An Empirical Study},
  year = {2002}
}

In this paper we present an approach to mapping and scheduling of distributed embedded systems for hard real-time applications, aiming at minimizing the system modification cost. We consider an incremental design process that starts from an already existing sys-tem running a set of applications. We are interested to implement new functionality so that the already running applications are dis-turbed as little as possible and there is a good chance that, later, new functionality can easily be added to the resulted system. The mapping and scheduling problem are considered in the context of a realistic communication model based on a TDMA protocol.

@inproceedings{Pop:2001ab,
  author = {Paul Pop and Petru Eles and Traian Pop and Zebo Peng},
  title = {Minimizing System Modification in an Incremental Design Approach},
  booktitle = {International Symposium on Hardware/Software Codesign},
  year = {2001},
  doi = {10.1109/HSC.2001.924672},
  url = {http://dx.doi.org/10.1109/HSC.2001.924672}
}

In this paper we present an approach to incremental design of distributed embedded systems for hard real-time applications. We start from an already existing system running a set of applications and the design problem is to implement new functionality on this system. Thus, we propose mapping strategies of functionality so that the already running functionality is not disturbed and there is a good chance that, later, new functionality can easily be mapped on the resulted system. The mapping and scheduling for hard real-time embedded systems are considered the context of a realistic communication model. Several experiments demonstrate the efficiency of the approach.

@inproceedings{Pop:2001aa,
  author = {Paul Pop and Petru Eles and Traian Pop and Zebo Peng},
  title = {An Approach to Incremental Design of Distributed Embedded Systems},
  journal = {A C M / I E E E Design Automation Conference. Proceedings},
  booktitle = {Design Automation Conference},
  publisher = {IEEE},
  year = {2001}
}

In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible; to generate a logically and temporally deterministic schedule; and to optimize parameters of the communication protocol such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only do particularities of the underlying architecture have to be considered during scheduling but also the parameters of the communication protocol should be adapted to fit the particular embedded application. The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.

@article{Eles:2000aa,
  author = {Petru Eles and Alex Doboli and Paul Pop and Zebo Peng},
  title = {Scheduling with Bus Access Optimization for Distributed Embedded Systems},
  journal = {IEEE Transactions on VLSI Systems},
  publisher = {I E E E},
  year = {2000},
  doi = {10.1109/92.894152},
  url = {http://dx.doi.org/10.1109/92.894152}
}

Is this paper we present an approach to schedulability analysis for hard real-time systems with control and data dependencies. We consider distributed architectures consisting of multiple programmable processors, and the scheduling policy is based on a static priority preemptive strategy! Our model of the system captures bath data and control dependencies, and the schedulability approach is able to reduce the pessimism of the analysis by using the knowledge about control ann data dependencies. Extensive experiments as well as a real life example demonstrate the efficiency of our approach.

@inproceedings{Pop:2000aa,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Schedulability Analysis for Systems with Data and Control Dependencies},
  journal = {Euromicro Conference on Real-Time Systems. Proceedings},
  booktitle = {Euromicro Conference on Real-Time Systems},
  publisher = {I E E E Computer Society},
  year = {2000},
  doi = {10.1109/EMRTS.2000.854008},
  url = {http://dx.doi.org/10.1109/EMRTS.2000.854008}
}

In this paper we present an approach to performance estimation for hard real-time systems. We consider architectures consisting of multiple processors. The scheduling policy is based on a preemptive strategy with static priorities. Our model of the system captures both data and control dependencies, and the analysis is able to reduce the pessimism of the estimation by using the knowledge about these dependencies. Extensive experiments as well as a real life example demonstrate the efficiency of our approach.

@inproceedings{Pop:2000ad,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Performance Estimation for Embedded Systems with Data and Control Dependencies},
  booktitle = {International Workshop on Hardware/Software Codesign},
  year = {2000}
}

We present an approach to bus access optimization and schedulability analysis for the synthesis of hard real-time distribution embedded systems. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays proposing four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the bus access scheme are developed, and the four approaches to message scheduling are compared using extensive experiments.

@inproceedings{Pop:2000ac,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis},
  booktitle = {Conference on Design, Automation and Test in Europe},
  publisher = {IEEE},
  year = {2000},
  doi = {10.1109/DATE.2000.840842},
  url = {http://dx.doi.org/10.1109/DATE.2000.840842}
}

We present an approach to process scheduling for synthesis of safety-critical distributed embedded systems.Our system model captures both the flow of data and that of control. The communication model is based on a time-triggered protocol. We take into consideration overheads due to communication and the execution environment.Communications have been optimized thr ough packaging of messages into slots with a pr operly selected order andlengths. Several experiments demonstrate the efficiency of the approach.

@inproceedings{Pop:1999ad,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Scheduling with Optimized Communication for Time-Triggered Embedded Systems},
  booktitle = {Workshop on Hardware/Software Codesign},
  publisher = {IEEE},
  year = {1999},
  doi = {10.1109/HSC.1999.777428},
  url = {http://dx.doi.org/10.1109/HSC.1999.777428}
}

We present an approach to static priority preemptive process scheduling for the synthesis of hard real-time distributed embedded systems where communication plays an important role. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays proposing four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the synthesis of communication are developed, and the four approaches to message scheduling are compared using extensive experiments

@inproceedings{Pop:1999ac,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems},
  booktitle = {International Conference on Real-Time Computing Systems and Applications},
  year = {1999},
  doi = {10.1109/RTCSA.1999.811257},
  url = {http://dx.doi.org/10.1109/RTCSA.1999.811257}
}

@inproceedings{Pop:1999ab,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Communication Scheduling for Time-Triggered Systems},
  journal = {Euromicro Conference on Real-Time Systems. Proceedings},
  booktitle = {Euromicro Conference on Real-Time Systems},
  publisher = {I E E E Computer Society},
  year = {1999},
  url = {http://www.informatik.uni-trier.de/\textasciitilde{}ley/db/conf/ecrts/ecrts1999.html}
}

In this paper we present an improved scheduling technique for the synthesis of time-triggered embedded systems. Our system model captures both the flow of data and that of control. We have considered communication of data and conditions for a time-triggered protocol implementation that supports clock synchronization and mode changes. We have improved the quality of the schedules by introducing a new priority function that takes into consideration the communication protocol. Communication has been optimized through packaging messages into slots with a properly selected order and lengths. Several experiments and a real-life example demonstrate the efficiency of our approach.

@inproceedings{Pop:1999aa,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {An Improved Scheduling Technique for Time-Triggered Embedded Systems},
  journal = {Euromicro Conference. Proceedings},
  booktitle = {Euromicro Conference on Real-Time Systems},
  publisher = {IEEE},
  year = {1999},
  doi = {10.1109/EURMIC.1999.794485},
  url = {http://dx.doi.org/10.1109/EURMIC.1999.794485}
}

We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

@inproceedings{Eles:1998ab,
  author = {Petru Eles and Krzysztof Kuchcinski and Zebo Peng and Paul Pop and Alex Doboli},
  title = {Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems},
  booktitle = {Conference on Design, Automation and Test in Europe},
  publisher = {Springer},
  year = {1998},
  doi = {10.1109/DATE.1998.655847},
  url = {http://dx.doi.org/10.1109/DATE.1998.655847}
}

In this paper we present an algorithm for system level hardware/software partitioning of heterogeneous embedded systems. The system is represented as an abstract graph which captures both data-flow and the flow of control. Given an architecture consisting of several processors, ASICs and shared busses, our partitioning algorithm finds the partitioning with the smallest hardware cost and is able to predict and guarantee the performance of the system in terms of worst case delay.

@inproceedings{Pop:1998aa,
  author = {Paul Pop and Petru Eles and Zebo Peng},
  title = {Scheduling Driven Partitioning of Heterogeneous Embedded Systems},
  booktitle = {Swedish Workshop on Computer Systems Architecture},
  year = {1998}
}

The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have developed algorithms for process graph scheduling based on listscheduling and branch-and-bound strategies. One essential contribution is in the manner in which information on process allocation is used in order to efficiently derive a good quality or optimal schedule. Experiments show the superiority of these algorithms compared to previous approaches like critical-path heuristics and ILP based optimal scheduling. An extension of our approach allows the scheduling of conditional process graphs capturing both data and control flow. In this case a schedule table has to be generated so that the worst case delay is minimized.

@inproceedings{Eles:1998aa,
  author = {Petru Eles and Krzysztof Kuchcinski and Zebo Peng and Alex Doboli and Paul Pop},
  title = {Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems},
  booktitle = {Euromicro Conference},
  publisher = {IEEE},
  year = {1998},
  doi = {10.1109/EURMIC.1998.711792},
  url = {http://dx.doi.org/10.1109/EURMIC.1998.711792}
}