Objectives	The objective of this project is to investigate optimal design under the presence of static gate leakages, and to device how design rules and trade-offs are altered.
Description	A main concern during the design of System-on Chips (SOCs) is the power budget, especially battery supplied systems are considered. In general, dynamic and static contributions constitute total power dissipation. Dynamic power is primarily consumed by the information processing in the charging and discharging of internal capacitances. As such, dynamic power consumption is proportional to these capacitances, the switching frequency and the supply voltage. Static power consumption, on the other hand, is caused by leakage currents while the circuit is idle, i.e. not performing computations. One key attraction of CMOS is negligible static power consumption. However, with decreasing device sizes this property is no longer satisfied due to subtreshold conduction. The reason for this is that for smaller devices, supply voltages are reduced. For speed, this in turn forces a reduction in threshold voltages. As a consequence, transistors are no longer turned off satisfactorily, i.e. drain currents contribute significantly to power losses in the transistor non-conductive state. For a 0.13µm process, the static losses may constitute almost 50% of the total power consumption. The issue has been addressed by offering libraries of gates and cells in both low-VT and high-VT versions. This offers the option of fast, low-VT cells with high static power losses where timing is critical, and a slower, high-VT design for other parts. Traditional synthesis tools do not offer the means to optimize for multiple-VT libraries to reduce static power consumption. The solution, using such known synthesis tools, consists of synthesizing a design using a low-VT library, under the constraint that timing and performance requirements are met. Then, in a post-synthesis phase, the back-annotated circuit is analyzed with respect to power consumption and the circuit modified, replacing low-VT by high-VT library cells whereever possible. The update process does not involve any re-synthesis steps.
Organization	The project has been split into 3 MSc Thesis projects in a collaborative yet independent effort. One work focusses on the design of libraries offering various speed to power alternatives, a second project discusses the incorporation of static power consumption metrics in the synthesis process while the last work concentrates on the incorporation of static power consumption metrics in the synthesis process: Project 1027 Design of CMOS cell libraries for minimal leakage currents Jacob Gregers Hansen This thesis work addresses the design of logic families using different transistor configurations to realize libraries representing alternatives in the speed-power design space and under various technologies. This includes the generation of a 90nm library or better from an existing library, and the characterization of this library for use in a synthesis tool. Project 1026 Incorporating leakage current considerations in logic synthesis Michael Kristensen This thesis work addresses how to incorporate static power consumption as part of the synthesis process, utilizing the detailed output of a power simulation in the synthesis. A method for multiple-VT synthesis is derived, and the capability of the method is compared to the capabilities of the Synopsys design tool. Project 1028 Architectural aspects of design for low static power consumption Martin Hans This thesis work addresses the consequences of the availability of multiple-VT libraries at architectural level. This includes a re-evaluation of traditional, architectural level design choices with respect to static power losses.
Period	17.02.2004 - 13.08.2004
Supervisor	Flemming Stassen, Technical University of Denmark Peter Østergaard Nielsen, Vitesse Semiconductor Corporation, Denmark