Real-Time Systems and Computer Architecture Projects

This is a list of projects for Bachelor and Master projects, advanced computer architecture projects, or projects for special courses and fagprojekt.

The size or complexity of the project is categorized with stars:

That means, e.g., a three stars project is an interesting master project, but might also be considered as a group project for a course or as a (group) Bachelor project.

You are always welcome to propose your own ideas for a project.

Accelerator Interface for Patmos **

Patmos is a RISC processor for real-time systems. For performance and time predictability reasons often algorithms are implemented directly in hardware. This project is about extending Patmos with an interface standard for hardware accelerators (coprocessors). One interface to be explored is a command to the accelerator that may include two register values and a destination register number on a write and a register value (or more in sequence) on a read. This interface is mapped to two custom instructions. The interface shall be demonstrated with a small accelerator. References: RoCC interface of the Rocket/RISC-V project.

Programming Predictable Time Machines in Lingua Franca **

The goal of this project is to prototype a design practice in which programs come with iron-clad timing guarantees (see paper). Two critical aspects complicate the design and implementation of embedded systems: concurrency and timing. Neither of these aspects is modeled by a Turing machine, the bedrock of modern computing machinery. Concurrency models such as threads or actors complement the Turing model, but the use of these models tends to compromise the key property of the Turing Machine that makes programs testable: determinism. Timing, typically perceived as an emergent property in most computing systems, is difficult to make precise and repeatable due to hardware designs that use heuristics such as caches and branch predictors to optimize average performance. This is a reasonable choice given that, in ordinary software, timing is usually considered a performance criterion. But in embedded software, it is often a correctness criterion.

Precision Timed (PRET) machines [1] are microprocessor architectures that offer precise and repeatable execution times. Patmos is a PRET machine implementation developed at DTU with multicore support. While Patmos makes a strong case for the applicability of PRET, even in performance-critical applications, a good programming model for PRET machines has been lacking. A recently introduced deterministic concurrent model of computation, called reactors (see paper), features a semantic notion of time, making it an excellent candidate for programming PRET machines.

Lingua Franca (LF) ( is a metalanguage for the specification and composition of reactors. The LF compiler currently outputs C code that is executable using a runtime environment that is compatible with POSIX systems. The project would be to adapt the existing runtime and create a version that can run on a bare-iron Patmos multicore processor.

[1] S. A. Edwards and E. A. Lee, "The Case for the Precision Timed (PRET) Machine," 2007 44th ACM/IEEE Design Automation Conference, San Diego, CA, 2007, pp. 264-265. (paper)

Transactional Memory on T-CREST ***

Transactional memory (TM) is a promising mechanism for synchronizing access to shared data. TM is usually developed to optimize the average case. In this thesis a real-time TM (RTTM) will be developed within the T-CREST multicore platform that is optimized for real-tie systems. The project can start on a RTTM version for the multicore version of JOP. (Read up what Augsburg is doing.)

MicroPython on Patmos **

Python is a popular scripting language. With MicroPython it is possible to use it on resource constrained embedded systems such as Patmos. Port MicroPython to Patmos.

Optimizing the Method Cache of Patmos

Patmos contains a method cache. the slides from the cache lecture contain some ideas to improve the method cache: (1) Different replacement policies: there is more time to decide; (2) Don‘t keep short methods in the cache: load time is already hidden, pollutes the cache; (3) Hit detection: more time available, trade off: parallel vs. sequential

SD card interface to Patmos **

An SD card is a convenient storage device for embedded systems. Within our Patmos processor project ( we are missing a file system. The project is to interface an SD card to Patmos and writing or porting a simple file system library for Patmos.

DDR controller for the DE2-115 ***

We have a working version in VHDL. However, we are aiming for a full Chisel project. This is a VHDL to Chisel porting project.

JTAG UART for Download

Intel FPGAs contain a JTAG UART that can be used with the NIOS to download programs. This project shall explore if this UART can also be used by other softcores, such as Patmos.

JavaScript on Patmos **

Patmos is a processor for embedded real-time systems, which often execute on the bare metal without an operating system ( Such applications are often written in C and C has the usual issues of a low-level language. Using a scripting language for at least part of the application improves the safety of the application. Within this thesis project a JavaScript runtime is ported for Patmos and an example application executing on an FPGA demonstrates the system. As an extension the Accessor project, which uses JavaScript, for the future Internet-of-Things can be explored.

Argo NoC in Chisel **

The Argo NoC was originally written in VHDL. Port the Argo NoC to Chisel so we can simulate it together with the Patmos processors.

Calvin on the Patmos Multicore **

Clavin is a data-flow coordination language. The project shall explore how to map the data-flow elements of a Patmos multicore with the Argo NoC. See

ORCC was for a long time the most-used compiler for CAL:

The people working on it maintain also a repository of application code (including a number of video decoders):

An alternative tool is OpenDF (long inactive)...

At EPFL, Endri Bezati has been working on synthesizing CAL programs to hardware, his project is called "streamblocks":

The MPEG effort that ended up adopting CAL is called "Reconfigurable Video Coding", RVC. Actually, they adopted a reduced version of the language, dubbed "RVC-CAL":

Someone compiled a list of related publications --- not really current, but might still be a good starting point:

Porting of a Real-Time Operating System to the T-CREST Platform ***

T-CREST is a research project on time-predictable multiprocessing. In this Master thesis an RTOS (such as FreeRTOS) will be ported to the processor Patmos and the T-CREST platform.

Neural Network **

Add a neural network accelerator to Patmos.

Roll Your Own Microprocessor **

Design you own microprocessor from scratch including an assembler. The processor needs to be pipelined

Network-on-chip in Chisel **

A standard NoC with standard wormhole routing

Floating-Point Unit for Patmos *

Patmos implements floating point operations in software. This project shall a FPU to Patmos. One option is to integrate the Berkeley hardfloat into Patmos and compare

2nd level cache **

Patmos multicore processor with shared L2 cache and cache coherence to L1.

VGA controller *

Add a VGA controller with software support to Patmos.

uCLinux on Patmos **

Patmos is a processor optimized for real-time systems. It is a time-predictable RISC processor. The current application environment is executing applications written in C on bare metal. uCLinux is a stripped down version of Linux that is intended for micro controllers. The proposed project is to port uCLinux to Patmos.

Measurement based WCET Analysis ***

Add performance counter to Patmos and use it for hybrid measurement and static WCET analysis.

Trace port for Patmos **

Add a trace port to Patmos (performance counters, including cache misses, memory,...)

Debugger for Patmos **

Add debugging support for Patmos (gdb)

Memory Arbiter for Mixed Real-Time Systems **

Round robin arbiter with rate control (for mixed real-time systems)

Real-time TCP/IP stack with WCET analysis ***

SWEET analysis tool integration ***

SWEET is a Swedish high level WCET analysis and Patmos is supported by the lower-level WCET analysis tool platin. the project is about combining those two tools.

Out-of-order Patmos ***

Implement an out-of-order version of Patmos. Can this still be time-predictable?

newlib Port to Leros **

Leros is an open-source processor with a simple accumulator architecture (see Leros includes a C compiler, a port of LLVM. To enable to write standard C, a port of the standard C library is needed. This bachelor project shall port newlib to Leros. Teaching Basic Computer Organization with Leros

Leros is an open-source processor with a simple accumulator architecture (see The instruction set of Leros can be presented on one page. Therefore, Leros is a good candidate for teaching basic computer organization (e.g., in courses such as 02132 and 02135). This bachelor project shall prepare teaching material to use Leros in an introductory bachelor course. The material shall become open-source as part of the Leros project.

Rust Compiler for Leros ***

Rust is a new language designed for safe concurrency and also optimized for small embedded systems ( Leros is an open-source processor with a simple accumulator architecture optimized for embedded systems (see The distribution of Leros contains an LLVM based C compiler. And Rust is based on LLVM. The bachelor project is on combining the Rust frontend of LLVM with the backend for Leros.

Rust Compiler for Patmos

Rust is a new language designed for safe concurrency and also optimized for small embedded systems ( Patmos is an open-source processor optimized for real-time systems ( The distribution of Patmos contains an LLVM based C compiler. And Rust is based on LLVM. The bachelor project is on combining the Rust frontend of LLVM with the backend for Patmos.

JavaScript Simulator of Patmos **

Patmos is a processor for embedded real-time systems, developed here at DTU and used in advanced computer architecture teaching. The project is to develop a Patmos instruction set simulator in JavaScript so it can execute in any browser. This project should be similar to the Venus RISC-V simulator at A useful tool will be:

WCET Analyzer for Patmos ***

Patmos is a time-predictable processor that is especially designed to simplify worst-case execution time (WCET) analysis, see The project is about to design a WCET analyzer that targets the Patmos architecture. This project can build on a tool called platin that supports some of the WCET analysis already. It can be an extension of platin, or a rewrite from scratch.

Patmos compiler optimization for dual issues ***

The current version of the LLVM compiler for Patmos is not very optimized for the dual-issue of Patmos ( The dual-issue version of Patmos is just about 10% faster than the single-issue version. Software pipelining and superblock scheduling should increase the performance by by an estimated 30% when the program is not memory bound.

RISC-V on the DE2-115 FPGA *

Implementation of the RISC-V Rocket chip on the DE2-115 FPGA board. The standard distribution o Rocket uses a Zynq board and help from the ARM processor to start. This project is about untethering Rocket and make it boot without the help of an additional processor.

OCaml on Patmos **

OCaml has been ported to a Raspberry Pi (, so it should be possible to execute it on Patmos.

A multithreaded Patmos (to compare against CMP/VLIW) ***

Explore Scala for RTS **

Enhance TiCOS to support multiple cores and to use the Argo NoC **

Compare OpenSoC with Argo **

CompCert C backend for Patmos ***

TinyOS on Patmos *

TinyOS is a small operating system mainly for wireless sensor network nodes. As it is a very small OS it is a very good fit for an embedded processor like Patmos. Patmos is a small real-time processor that can be a good architecture for low-power devices. The project is about porting this OS to Patmos and exploring it with small examples. Optionally the TinyOS functions can be analyzed for the worst-case execution time (WCET) with the WCET analysis tool of Patmos.

A Simple Hardware Simulation Framework **

One of the standard frameworks for hardware simulation is SystemC. However, SystemC is quite verbose and an overkill for the simulation of simple pipelines (such as a processor). In the project a simple simulation framework for pipelined hardware shall be developed in Java or Scala. The main focus is on a small, easy to use framework and not on many features. As evaluation of the framework the Patmos VLIW processor shall be implemented on top of the framework.