This is a list of projects for Bachelor and Master projects, advanced computer architecture projects, or projects for special courses.
Contact Martin Schoeberl.
The size or complexity of the project is categorized with stars:
That means, e.g., a three stars project is an interesting master project, but might also be considered as a group project for a course or as a (group) Bachelor project.
You are always welcome to propose your own ideas for a project.
Wildcat is a 3-stage pipeline implementation of the RISC-V instruction set. To build a complete microcontroller several components need to be added: cache, memory controller, SPI based Flash and SRAM controller, and probably more. The aim of the project is to produce a real chip with ChipFoundry.io.
Patmos is a time-predictable processor that is especially designed to simplify worst-case execution time (WCET) analysis. Similar Wildcat is a RISC-V processor aiming for real-time systems.
The project is about to design a WCET analyzer that targets the Patmos architecture. This project can build on a tool called platin that supports some of the WCET analysis already. It can be an extension of platin, or a rewrite from scratch, e.g., in Scala to better fit the Chisel implementations
Platin, our WCET analysis tool, is missing a standard data cache analysis.
Platin, our WCET analysis tool, is missing a standard instruction cache analysis.
Patmos multicore processor with shared L2 cache and cache coherence to L1.
With yosys and further tools it is now possible to design and verify a chip with open-source tools only. Furthermore, Google sponsors the production of chips in a multi-project waver, if the design is in open-source. This project is about exploring the design flow using Patmos/T-CREST and getting a real chip produced by Google.
Chisel, a modern hardware construction language, includes a testing framework to write simple unit tests. However, it lacks more advanced verification tools, as they can be found in SystemVerilog and UVM. This project is aiming to fill this gap a provide support for constraint random verification, co-simulation, and test coverage measurements within a modern language, such as Java and Scala. The verification framework shall also be usable with Verilog and VHDL designs.
Chisel, a modern hardware construction language, supports testing with simple assertions. However, for more complex hardware designs, assertions that cover also time relationships are a good tool for debugging and testing. This project will add timed assertions, like those that are found in SystemVerilog, to the Chisel testing and verification framework chiselverify.
The current possibilities to test Chisel hardware are a FIRRTL interpreter (Treadle) or converting the design to Verilog and execute it on Verilator. The Treadle version has a quick startup time, but is slow. The Verilator version has a higher startup time (generating C code and compiling it), but has a faster simulation. However, to drive the Verilator simulation from ChiselTest, ChiselTest still needs to cross the language barrier between the JVM and C library. This project shall optimize this by generating on the fly a JVM bytecode representation of the circuit and dynamically loading it for simulation.
Reactors are a new form to organize real-time applications. They also offer a way to specify concurrency. In this project the task is to use a network-on-chip to explore the concurrency of LF actors. See: https://github.com/icyphy/lingua-franca
Transactional memory (TM) is a promising mechanism for synchronizing access to shared data. TM is usually developed to optimize the average case. In this thesis a real-time TM (RTTM) will be developed within the T-CREST multicore platform that is optimized for real-tie systems. The project can start on a RTTM version for the multicore version of JOP. (Read up what Augsburg is doing.)
Python is a popular scripting language. With MicroPython it is possible to use it on resource constrained embedded systems such as Patmos. Port MicroPython to Patmos.
Patmos contains a method cache. the slides from the cache lecture contain some ideas to improve the method cache: (1) Different replacement policies: there is more time to decide; (2) Don‘t keep short methods in the cache: load time is already hidden, pollutes the cache; (3) Hit detection: more time available, trade off: parallel vs. sequential
We have a working version in VHDL. However, we are aiming for a full Chisel project. This is a VHDL to Chisel porting project.
Intel FPGAs contain a JTAG UART that can be used with the NIOS to download programs. This project shall explore if this UART can also be used by other softcores, such as Patmos.
Patmos is a processor for embedded real-time systems, which often execute on the bare metal without an operating system (http://patmos.compute.dtu.dk/). Such applications are often written in C and C has the usual issues of a low-level language. Using a scripting language for at least part of the application improves the safety of the application. Within this thesis project a JavaScript runtime is ported for Patmos and an example application executing on an FPGA demonstrates the system. As an extension the Accessor project, which uses JavaScript, for the future Internet-of-Things can be explored.
T-CREST is a research project on time-predictable multiprocessing. In this Master thesis an RTOS (such as FreeRTOS) will be ported to the processor Patmos and the T-CREST platform.
A standard NoC with standard wormhole routing
Patmos implements floating point operations in software. This project shall a FPU to Patmos. One option is to integrate the Berkeley hardfloat into Patmos and compare https://github.com/ucb-bar/berkeley-hardfloat/blob/master/README.md
Patmos is a processor optimized for real-time systems. It is a time-predictable RISC processor. The current application environment is executing applications written in C on bare metal. uCLinux is a stripped down version of Linux that is intended for micro controllers. The proposed project is to port uCLinux to Patmos.
Round robin arbiter with rate control (for mixed real-time systems)
Continue the work started in iot-rt, see also paper.
Leros is an open-source processor with a simple accumulator architecture (see https://leros-dev.github.io/). Leros includes a C compiler, a port of LLVM. To enable to write standard C, a port of the standard C library is needed. This bachelor project shall port newlib to Leros. Teaching Basic Computer Organization with Leros
Leros is an open-source processor with a simple accumulator architecture (see https://leros-dev.github.io/). The instruction set of Leros can be presented on one page. Therefore, Leros is a good candidate for teaching basic computer organization (e.g., in courses such as 02132 and 02135). This bachelor project shall prepare teaching material to use Leros in an introductory bachelor course. The material shall become open-source as part of the Leros project.
Rust is a new language designed for safe concurrency and also optimized for small embedded systems (https://www.rust-lang.org/en-US/). Leros is an open-source processor with a simple accumulator architecture optimized for embedded systems (see https://leros-dev.github.io/). The distribution of Leros contains an LLVM based C compiler. And Rust is based on LLVM. The bachelor project is on combining the Rust frontend of LLVM with the backend for Leros.
Rust is a new language designed for safe concurrency and also optimized for small embedded systems (https://www.rust-lang.org/en-US/). Patmos is an open-source processor optimized for real-time systems (http://patmos.compute.dtu.dk/). The distribution of Patmos contains an LLVM based C compiler. And Rust is based on LLVM. The bachelor project is on combining the Rust frontend of LLVM with the backend for Patmos.