This is a list of projects for Bachelor and Master projects, advanced computer architecture projects, or projects for special courses and fagprojekt.
The size or complexity of the project is categorized with stars:
That means, e.g., a three stars project is an interesting master project, but might also be considered as a group project for a course or as a (group) Bachelor project.
You are always welcome to propose your own ideas for a project.
Within the PREDICT project we have built a drone and a multicore drone controller hardware. The task is to write/port a drone controlling software that is time-predictable. Furthermore, it should be explored how this controller software can be partitioned for multiple cores and using a real-time communication via the Argo network-on-chip.
Design and build RISC-V processor supporting vector extension and optionally test this in FPGA platform. This project is in cooperation with Comcores.
An FPGA is a good device to build custom hardware therefore an interesting platform for audio processing. This can be simple sigma-delta AD and DA converters using just resistors and capacitors. Or you can attach a commercial AD/DA converter to your Basys 3 board and implement sound processing and sound effects on that board.
In CAE you have built an instruction set simulation of a RISC-V processor. Now it is time to build a real RISC-V microprocessor in an FPGA (e.g., on the Basys 3 board). There are two possibilities to implement a microprocessor: (1) you chose to implement it as a finite state machine with a datapath or (2) as a more advanced version with a 5-stage pipeline, including forwarding.
With yosys and further tools it is now possible to design and verify a chip only with open-source tools. Furthermore, Google sponsors the production of chips in a multi-project waver, if the design is in open-source. This project is about exploring the design flow using Patmos/T-CREST and getting a real chip produced by Google
Chisel, a modern hardware construction language, includes a testing framework to write simple unit tests. However, it lacks more advanced verification tools, as they can be found in SystemVerilog and UVM. This thesis/project is aiming to fill this gap a provide support for constraint random verification, co-simulation, and test coverage measurements. This project will contribute to chiselverify.
Chisel, a modern hardware construction language, supports testing with simple assertions. However, for more complex hardware designs, assertions that cover also time relationships are a good tool for debugging and testing. This project will add timed assertions, like those that are found in SystemVerilog, to the Chisel testing and verification framework chiselverify.
The current possibilities to test Chisel hardware are a FIRRTL interpreter (Treadle) or converting the design to Verilog and execute it on Verilator. The Treadle version has a quick startup time, but is slow. The Verilator version has a higher startup time (generating C code and compiling it), but has a faster simulation. However, to drive the Verilator simulation from ChiselTest, ChiselTest still needs to cross the language barrier between the JVM and C library. This project shall optimize this by generating on the fly a JVM bytecode representation of the circuit and dynamically loading it for simulation.
A master project added several audio effects to the Patmos project. The project is about extracting those components and integrating them into the soundbytes framework and testing them with Patmos.
The goal of this project is to prototype a design practice in which programs come with iron-clad timing guarantees (see paper). Two critical aspects complicate the design and implementation of embedded systems: concurrency and timing. Neither of these aspects is modeled by a Turing machine, the bedrock of modern computing machinery. Concurrency models such as threads or actors complement the Turing model, but the use of these models tends to compromise the key property of the Turing Machine that makes programs testable: determinism. Timing, typically perceived as an emergent property in most computing systems, is difficult to make precise and repeatable due to hardware designs that use heuristics such as caches and branch predictors to optimize average performance. This is a reasonable choice given that, in ordinary software, timing is usually considered a performance criterion. But in embedded software, it is often a correctness criterion.
Precision Timed (PRET) machines  are microprocessor architectures that offer precise and repeatable execution times. Patmos is a PRET machine implementation developed at DTU with multicore support. While Patmos makes a strong case for the applicability of PRET, even in performance-critical applications, a good programming model for PRET machines has been lacking. A recently introduced deterministic concurrent model of computation, called reactors (see paper), features a semantic notion of time, making it an excellent candidate for programming PRET machines.
Lingua Franca (LF) (https://github.com/icyphy/lingua-franca) is a metalanguage for the specification and composition of reactors. The LF compiler currently outputs C code that is executable using a runtime environment that is compatible with POSIX systems. The project would be to adapt the existing runtime and create a version that can run on a bare-iron Patmos multicore processor.
 S. A. Edwards and E. A. Lee, "The Case for the Precision Timed (PRET) Machine," 2007 44th ACM/IEEE Design Automation Conference, San Diego, CA, 2007, pp. 264-265. (paper)
Reactors are a new form to organize real-time applications. They also offer a way to specify concurrency. In this project the task is to use a network-on-chip to explore the concurrency of LF actors. See: https://github.com/icyphy/lingua-franca
Transactional memory (TM) is a promising mechanism for synchronizing access to shared data. TM is usually developed to optimize the average case. In this thesis a real-time TM (RTTM) will be developed within the T-CREST multicore platform that is optimized for real-tie systems. The project can start on a RTTM version for the multicore version of JOP. (Read up what Augsburg is doing.)
Python is a popular scripting language. With MicroPython it is possible to use it on resource constrained embedded systems such as Patmos. Port MicroPython to Patmos.
Patmos contains a method cache. the slides from the cache lecture contain some ideas to improve the method cache: (1) Different replacement policies: there is more time to decide; (2) Don‘t keep short methods in the cache: load time is already hidden, pollutes the cache; (3) Hit detection: more time available, trade off: parallel vs. sequential
We have a working version in VHDL. However, we are aiming for a full Chisel project. This is a VHDL to Chisel porting project.
Intel FPGAs contain a JTAG UART that can be used with the NIOS to download programs. This project shall explore if this UART can also be used by other softcores, such as Patmos.
The Argo NoC was originally written in VHDL. Port the Argo NoC to Chisel so we can simulate it together with the Patmos processors. Within this project you can compare the efficiency of VHDL and Chisel.
Clavin is a data-flow coordination language. The project shall explore how to map the data-flow elements of a Patmos multicore with the Argo NoC. See https://ptolemy.berkeley.edu/papers/03/Cal/
ORCC was for a long time the most-used compiler for CAL: https://sourceforge.net/projects/orcc/
The people working on it maintain also a repository of application code (including a number of video decoders): https://github.com/orcc/orc-apps
An alternative tool is OpenDF (long inactive)... https://sourceforge.net/p/opendf
At EPFL, Endri Bezati has been working on synthesizing CAL programs to hardware, his project is called "streamblocks": https://github.com/streamblocks
The MPEG effort that ended up adopting CAL is called "Reconfigurable Video Coding", RVC. Actually, they adopted a reduced version of the language, dubbed "RVC-CAL": https://en.wikipedia.org/wiki/Reconfigurable_video_coding
Someone compiled a list of related publications --- not really current, but might still be a good starting point: http://www.hooklee.com/Research/RVC_CAL_Bibliography.html
T-CREST is a research project on time-predictable multiprocessing. In this Master thesis an RTOS (such as FreeRTOS) will be ported to the processor Patmos and the T-CREST platform.
Add a neural network accelerator to Patmos.
Design you own microprocessor from scratch including an assembler. The processor needs to be pipelined
A standard NoC with standard wormhole routing
Patmos implements floating point operations in software. This project shall a FPU to Patmos. One option is to integrate the Berkeley hardfloat into Patmos and compare https://github.com/ucb-bar/berkeley-hardfloat/blob/master/README.md
Patmos multicore processor with shared L2 cache and cache coherence to L1.
Add a VGA controller with software support to Patmos.
Patmos is a processor optimized for real-time systems. It is a time-predictable RISC processor. The current application environment is executing applications written in C on bare metal. uCLinux is a stripped down version of Linux that is intended for micro controllers. The proposed project is to port uCLinux to Patmos.
Add performance counter to Patmos and use it for hybrid measurement and static WCET analysis.
Add a trace port to Patmos (performance counters, including cache misses, memory,...)
Add debugging support for Patmos (gdb)
Round robin arbiter with rate control (for mixed real-time systems)
Continue the work started in iot-rt, see also paper.
SWEET is a Swedish high level WCET analysis and Patmos is supported by the lower-level WCET analysis tool platin. the project is about combining those two tools.
Implement an out-of-order version of Patmos. Can this still be time-predictable?
Leros is an open-source processor with a simple accumulator architecture (see https://leros-dev.github.io/). Leros includes a C compiler, a port of LLVM. To enable to write standard C, a port of the standard C library is needed. This bachelor project shall port newlib to Leros. Teaching Basic Computer Organization with Leros
Leros is an open-source processor with a simple accumulator architecture (see https://leros-dev.github.io/). The instruction set of Leros can be presented on one page. Therefore, Leros is a good candidate for teaching basic computer organization (e.g., in courses such as 02132 and 02135). This bachelor project shall prepare teaching material to use Leros in an introductory bachelor course. The material shall become open-source as part of the Leros project.
Rust is a new language designed for safe concurrency and also optimized for small embedded systems (https://www.rust-lang.org/en-US/). Leros is an open-source processor with a simple accumulator architecture optimized for embedded systems (see https://leros-dev.github.io/). The distribution of Leros contains an LLVM based C compiler. And Rust is based on LLVM. The bachelor project is on combining the Rust frontend of LLVM with the backend for Leros.
Rust is a new language designed for safe concurrency and also optimized for small embedded systems (https://www.rust-lang.org/en-US/). Patmos is an open-source processor optimized for real-time systems (http://patmos.compute.dtu.dk/). The distribution of Patmos contains an LLVM based C compiler. And Rust is based on LLVM. The bachelor project is on combining the Rust frontend of LLVM with the backend for Patmos.
Patmos is a time-predictable processor that is especially designed to simplify worst-case execution time (WCET) analysis, see http://patmos.compute.dtu.dk/. The project is about to design a WCET analyzer that targets the Patmos architecture. This project can build on a tool called platin that supports some of the WCET analysis already. It can be an extension of platin, or a rewrite from scratch.
The current version of the LLVM compiler for Patmos is not very optimized for the dual-issue of Patmos (http://patmos.compute.dtu.dk/). The dual-issue version of Patmos is just about 10% faster than the single-issue version. Software pipelining and superblock scheduling should increase the performance by by an estimated 30% when the program is not memory bound.
Implementation of the RISC-V Rocket chip on the DE2-115 FPGA board. The standard distribution o Rocket uses a Zynq board and help from the ARM processor to start. This project is about untethering Rocket and make it boot without the help of an additional processor.
OCaml has been ported to a Raspberry Pi (https://github.com/dbuenzli/rpi-boot-ocaml), so it should be possible to execute it on Patmos.