02208 Test of Integrated Circuits
Assignment: Design for Test of Embedded Microprocessors

Embedded cores are an essential part in the realisation of complex, integrated Systems-On-Chip (SOC). Frequently, the design of an SOC relies on the use of a microprocessor core designed by a third party in the form of an Intellectual Property (IP).

In this problem, design for test considerations of such an embedded core is addressed with specific address to path delay testing. Typically, scan testing in either full scan or partial scan is implemented based on the IEEE 1149.1 boundary scan architecture.

Scan design primarily addresses testing of combinational faults. Accurate path delay testing of IC's is not immediately addressed. However, path delay testing may be combined with scan design.

Based on the literature below, the following issues must be discussed:

• Discuss the overall test objectives and design for test strategies for an embedded microprocessor such as the ColdFire core
• Explain the use of IEEE 1149.1 boundary scan design in the design of an embedded core
• Discuss the concepts of structurally testable delay paths and functionally testable paths

References

• A.L. Crouch, M. Mateja, T.L. McLaurin, J.C. Potter and D. Tran,
  `Test Development for a Third-Version ColdFire Microprocessor',
  IEEE Design & Test of Computers, Vol.17/4, October 2000, pp 29-37
• W-C. Lai, A. Krstic, and K-T. Cheng,
  `Functionally Testable Path Delay Faults on a Microprocessor',
  IEEE Design & Test of Computers, Vol.17/4, October 2000, pp 6-14

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[02208 homepage]       Modified by Flemming Stassen on 13 March 2001     stassen@imm.dtu.dk

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