02208 Test of Integrated Circuits
Assignment: Bridging faults

The traditional single stuck-at fault model is the most common fault model used for test pattern generation and fault simulation for integrated circuits. However, a large fraction of occuring physical defects in contemporary CMOS technologies are not correctly modeled, and must be modeled separately using different models.

Results from inductive fault analysis have demonstrated that the most commonly occuring type of faults resulting from fabrication defects is the bridging fault. However, shorts may be missed by test sets achieving full single stuck fault coverage. The inadequacy of the single stuck-at fault model implies that prediction of IC quality using only this model is not accurate.

To assure low defect levels, bridging defects must be covered by the production test sets. Quiescent power supply current (IDDQ) testing has been shown to be effective in CMOS bridging fault detection. However, the IDDQ test set is limited in size due to slow application rate. Therefore, logic-based test sets are generated for at-speed testing.

Based on the literature below, the following issues must be discussed:

• Discuss how shorts are modeled as bridging faults at circuit, gate, and switch levels
• Describe the principles of IDDQ testing with specific emphasis on test pattern generation and test application for bridging faults
• Explain the techniques used in logic-based test pattern generation for bridging faults
• Discuss the influence of undetectable shorts on test pattern generation, and how such undetectable shorts may be predicted

References

• M. Favalli, P. Olivo, M. Damiani, and B. Ricco,
  `Fault simulation of unconventional faults in CMOS circuits',
  IEEE TCAD-10/5, May 1991, pp 677-682
• S. D. Millman and E. J. McCluskey,
  `Detecting bridging faults with stuck-at test sets',
  1988 International Test Conference, pp 773-783
• J. C. Cusey and J. H. Patel,
  `BART: A Bridging Fault Test Generator for Sequential Circuits',
  1997 International Test Conference, pp 838-847
• T. Chen, I. N. Hajj, E. M. Rudnick, and J. H. Patel,
  `An Efficient I_DDQ Test Generation Scheme for Bridging Faults in CMOS Digital Circuits',
  1996 International Workshop on IDDQ Testing, pp 74-78
• E. Isern and J. Figueras,
  `Test of Bridging Faults in Scan-Based Sequential Circuits',
  1994 European Design and Test Conference, pp 366-370
• R. McGowen and F. Joel Ferguson,
  `A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical DFT',
  1994 European Design and Test Conference, pp 371-375

---

[02208 homepage]       Modified by Flemming Stassen on 7 October 2002     stassen@imm.dtu.dk

---