02208 Test of Integrated Circuits
Assignment: Partial scan design using IEEE 1149.1

Scan design is a well-established technique for design for testability. Scan design provides a methodology for adding test circuitry to an IC that allow at least a part of the internal state of the IC to be controlled and observed using the scan chain. The scan chain can be incorporated into the IEEE 1149.1 boundary scan design.

In scan design, the latches of the circuit are chained to form a linear shift register. All latches (full scan) or only a subset of latches (partial scan) may be chained. From a performance point of view, full scan design may be unacceptable. However, the selection of the scan elements for partial scan is not a trivial problem.

Scan design primarily addresses testing of combinational faults. Accurate path delay testing of IC's is not immediately addressed. However, path delay testing may be combined with scan design.

Based on the literature below, the following issues must be discussed:

• Discuss the potentials of scan design and how to combine partial scan design with IEEE 1149.1 boundary scan design
• Explain the basic design rules for partial scan design
• Describe how scan elements of a partial scan path may be selected
• Discuss how scan design may be used for delay testing

References

• M. Abramovici, M.A. Breuer and A.D. Friedman,
  `Some Advanced Scan Concepts',
  in `Digital Systems Testing and Testable Design',
  Computer Science Press, 1990, pp 385-395
• D.M. McCarthy, P.W. Hollis, R.J. Yu and R.L. Eisele,
  `Scan Based Path Delay Testing of Integrated Circuits Containing Embedded Memory Elements',
  US Patent 5,761,215, June 2, 1998
• A.L. Crouch, M. Mateja, T.L. McLaurin, J.C. Potter and D. Tran,
  `Test Development for a Third-Version ColdFire Microprocessor',
  IEEE Design & Test of Computers, Vol.17/4, October 2000, pp 29-37

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[02208 homepage]       Modified by Flemming Stassen on 13 March 2001     stassen@imm.dtu.dk

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