02208 Test of Integrated Circuits
Assignment: Delay test

Test of digital circuits implies verification of both functional and temporal behaviour of the circuits manufactured. Test targeted for stuck-at faults may be insufficient to guarantee an acceptable quality level, as some defects or perhaps random process variations will affect the dynamic, but not the steady state behaviour of the system.

Departure from correct temporal behaviour is frequently modeled by delay faults. Both gate-oriented and path-oriented fault models have been proposed for test generation and fault simulation. In both models, a delay fault has occured, when the delay falls outside certain, specified limits.

The gate delay fault model models faults that cause violations of the circuit specification at the outputs of gates. In the path delay fault model, the delay of a signal propagating along a path from primary inputs to primary outputs is considered, i.e. taking into account the sum of delays on an entire signal path.

Based on the literature below, the following issues must be discussed:

• Describe and compare the gate delay and path delay fault models
• Discuss the principles of test pattern generation for path delay faults, and explain how parallel test pattern generation can be implemented
• Discuss the use of random sampling times for delay fault testing and the impact on test hardware
• Define the concept of delay verification test sets, and discuss how delay verifiable circuits may be implemented

References

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[02208 homepage]       Modified by Flemming Stassen on 17 September 2002     stassen@imm.dtu.dk

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