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by Bilal K. Taherkheli, Christian P. Kjeldsen,
Asger Stenberg, and Felipe Rivera |
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Autumn 2002, 02208 Test of Integrated Circuits |
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Test objectives and DFT strategies |
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Using IEEE 1149.1 Boundary Scan |
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IEEE P1500 standard |
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Structural delay paths and functionally testable
paths |
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Better functional testability |
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Increase the quality of functional verification |
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Easier to test performance requirements |
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Other factors |
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Faster and better post fabrication tests |
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Higher quality ICs |
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Improve company reputation |
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Low cost |
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minimal area, 5 sec test time max, cheap ATE |
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Consistent methodology |
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Reuse for future products |
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Automation |
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ATPG, ATE, use of existing tools |
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Accountability |
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Measure fault coverage, specifications |
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Particular to the characteristics of the design |
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They, obviously, comply with the defined
objectives |
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The test engineer chooses among many
alternatives from the IC testing field |
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Core |
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RISC Processor |
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Embedded memory |
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Peripherals |
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All embedded cores portable and synthesizable |
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Based on the work for ColdFire V2 |
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Reused strategies |
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Path delay testing, At-speed scan, Iddq,
Scan-based burn-in |
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Some others dropped in favor of better ones |
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DMA-based memory testing -> MemoryBIST |
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Some others gone |
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Sequential testing |
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New design -> New features -> New
strategies … New Challenges! |
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Two clock domains |
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Internal PLL |
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Doubly embedded nature of the core memory |
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Two clock domain |
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Core at full speed (fastclk), peripherals at
fastclk/2 |
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ATE, I/O pads, ATPG limitations |
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Patterns from ATPG had to be post-processed |
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ATE pin multiplexing |
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Clock skew |
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Clock-Data races |
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Scan testing problems |
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V2 DMA-based testing Big interface |
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Design dependent |
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No possible to test the SRAM completely |
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Path delay couldn’t be performed completely |
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V3 MemoryBIST |
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Big area (4%) |
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More benefits than drawbacks |
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Core encapsulation |
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Retention test mechanism |
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Scan testing of the I/O (Flow-Through RAMs) |
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MemoryBIST |
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Two pauses for retention testing (instead of
six) |
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Only tests memory cells so there needs to be
additional logic to (flow-through memory) |
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Test inputs for stuck-at and path delay faults |
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Test outputs for stuck-at and transition faults
and path sensitization for path delay testing |
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Testing objectives for embedded microprocessors
can be reached with existing techniques |
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Time-to-market and economics are the driving
forces behind the defined objectives |
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A migration path to cheaper ATEs is a
requirement |
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New challenges for testing arise when different
clock domains are used |
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What your mother didn’t want you to know |
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Test architecture |
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Provide access and control to DFT structures |
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Internal scan, boundary scan, BIST, Emulation
features |
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Popular on stand-alone IC’s |
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Low pin count, versatile, easy to comply,
flexible. |
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Only ONE TAP per IC. |
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Components |
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TAP Controller, IR (Indicates what test to
perform), Data registers (test output data) |
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Technical limitations |
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Can’t apply it to SoC’s due to their modularity |
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Some IP-Cores have it, some don’t. |
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JTAG is a separate module, but still tightly
coupled with the core |
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Breaks the standard |
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Business and policies |
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Reluctant to change |
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Don't see the need |
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Own policies considered better than the standard |
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Cores designed to interface to a TAP (TAP1) |
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TAP’ed cores (TAP2, TAP3, TAP4) |
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BREAKS the standard |
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Not optimum |
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Not good for reuse |
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Many more AdHoc approaches… |
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IBM paper proposes a similar solution to allow
the use of existing development tools |
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Provides consistency in the way multiple IC’s in
a board are currently tested |
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Tap Linking Modules (TLMs) |
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Standard compliant |
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Adds a ‘layer’ to isolate the inner
singularities of the modules |
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G2 PowerPC 603e implements it |
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Enables background BIST |
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Still ALL TAPs must be modified and at least one
instruction has to be added |
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Need of a new standard for IP-Core use |
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P1500 |
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Another standard |
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Standard for Embedded Core Test |
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Yervant Zorian (Chair) |
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Erik Jan Marinissen (Chair of Compliance
Definition and Documentation) |
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Rohit Kapur (Chair of Core Test Language) |
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Maurice Lousberg |
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Teressa McLaurin |
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Mike Ricchetti |
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Core Test Language (CTL) |
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(Worked done in conjunction with the IEEE
1450.6 CTL which is an extension to the IEEE 1450.0 Standard Test Interface
Language (STIL)) |
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Wrapper |
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A thin shell around the core, which defines
a standard Core Test Access Point (CTAP) |
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TAM : Test Access Mechanism – no longer part of
the IEEE P1500, but it was intended in the beginning. A survey showed that
the testing internal of the Core, and the connections to the test access
mechanism at chip-level was not in demand from the companies. |
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Wrapper: |
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A method to switch between normal, internal
test, and external test mode. |
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Only thing considered in this presentation |
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WSI : Wrapper Serial Input |
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WSO : Wrapper Serial Output |
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WIP : Wrapper Interface Port |
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WIR : Wrapper Instruction register |
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WBR : Wrapper Boundary Register (made of Wrapper
Boundary Cells) |
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WBY : Wrapper Bypass Register |
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WPI : Wrapper Parallel Input (Optional) |
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WPO : Wrapper Parallel Output (Optional) |
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WRCK : Wrapper Clock, dedicated clk for
registers |
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WRSTN : Wrapper Reset, dedicated active-low
reset signal |
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SelectWIR : Selects the WIR register when high.
Otherwise either WBR, WBY or any other core-internal register can be chosen
depending on the Instruction. |
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ShiftWR, UpdateWR, and CaptureWR : Explained on
the next slide. |
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ShiftWR : Shifts the wrapper register chosen |
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UpdateWR : Updates the wrapper register chosen |
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CaptureWR : What do you think it does? |
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So why do we need these three signals? |
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No FSM as is well-known from IEEE 1149.1 in the
IEEE P1500 |
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Instead the WIR register is split in two: WIR
Shift Register and WIR Update Register |
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Normal / Serial Bypass |
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Serial In Test |
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Serial Ex Test |
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Parallel In test |
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Parallel Ex Test |
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Others |
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But I’ll not go through the exact instructions |
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Only serial connections of wrappers intended
(i.e. hierarchy is not really supported) |
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If cores with other Test Access Mechanisms are
used (e.g. JTAG) in combination with the P1500, some functionality is lost. |
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The connection to a chip level JTAG module not
defined |
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IEEE P1500 standard meets the stated goal. |
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However, some people thinks the goals are not
the right ones. |
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What the standard of the future will be is
uncertain. |
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PROBLEM |
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Technology is advancing rapidly with more
transistors per chip and higher operating speeds but tester’s speed is not
increasing at the same rate; affecting delay testing of microprocessors |
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SOLUTION |
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An increased trend to employ BIST techniques |
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Advantages |
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good test quality |
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at speed
testing |
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greater
accuracy than the tester |
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Disadvantages |
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increased chip area |
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reduced
performance |
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increased design time overhead |
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higher
power consumption |
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(non functional random switching) |
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A path is structurally testable if there exists
a test vector pair applied through enhanced or standard full scan chain,
which sensitizes the path. |
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Enhanced scan structurally testable (all
detectable faults can be tested ) |
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Full scan structurally testable (not all vector
pairs can be applied) |
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Do we really NEED all this fancy stuff for
testing a microprocessor? |
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NO |
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Functional Test |
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Use instruction sequences (functional vectors)
as test vectors |
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Reduced set of test vectors |
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A path is functionally testable if there exists
a functional test for that path, otherwise its functionally untestable. |
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A functionally untestable path cannot be tested
by any instruction sequence |
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Classification of path delay fault |
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Enhanced scan structurally testable |
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Full scan structurally testable |
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Functionally testable |
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In functional testing certain temporal and
spatial correlations are imposed among registers/flip- flops and thus among
inputs/outputs of the embedded block of the processor |
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Not all paths are functionally testable even if
they are structurally testable |
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whenever there is a falling transition on S1, AC
and IR can never be enabled in the following cycle |
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Realistic fault coverage |
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Reduced test generation effort |
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Appropriate path selection in delay testing |
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Identification of true critical paths |
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Help in
synthesis process |
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Wow – we are almost finished |
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Some test objectives have been stated. |
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A case study of DFT for a microprocessor core
has been made. |
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The use of IEEE 1149.1 in connection with
embedded cores has been discussed |
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Parts of the IEEE P1500 has been presented |
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The use of functionally testable delay paths
over structurally testable delay paths has been addressed |
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Spend a good deal of your time today |
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Stassen & Stassen |
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I test you! |
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