02208 Test of Integrated Circuits
Presentation Schedule '2
Presentations 29 November 2002:
Low-Power Testing
Presentation 15:
8 30 - 9 30
to be determined
Presentation by: Xin Meng
Critique by: Kehuai Wu
Literature:
P. Girard,
`Survey of low-power testing of VLSI circuits',
IEEE Design & Test of Computers, Vol.19/3, May 2002, pp 82-92
(Paper 20: to be downloaded from Campusnet)
Presentations 22 November 2002:
BIST for SOCs (2)
Presentation 14:
8 30 - 9 30
BIST for SOCs (2)
Presentation by: Asger Stenberg Pedersen
Critique by: Ryan Mitchell Raasch
Literature:
A. Benso, S. Chiusano, G. di Natale, P. Prinetto and M.L. Bondoni,
`Online and Offline BIST in IP-Core Design',
IEEE Design & Test of Computers, Vol.18/5, November 2001, pp 92-98
(Paper 18: to be downloaded from Campusnet)
Presentations 15 November 2002:
Presentation 13:
8 30 - 9 30
BIST for SOCs (1)
Presentation by: Nicolai Ascanius Jørgensen
Critique by: Andreas Vad Lorentzen
Literature:
A. Chandra and K. Chakrabarty,
`Test Resource Partitioning for SOCs',
IEEE Design & Test of Computers, Vol.18/5, November 2001, pp 80-90
(Paper 17: to be downloaded from Campusnet)
Presentations 8 November 2002:
Presentation 12:
8 30 - 9 30
Concurrent Error Detection
Presentation by: Jon Kaare Christiansen
Critique by: Michael Kristensen
Literature:
Concurrent Error Detection Using Signature Monitoring and
Encryption,
K. Wilken and J.P. Shen, in Dependable Computing for Critical Applications,
A. Avizienis and J.C. Laprie (editors),
Springer-Verlag 1991, pp 365-384
(Paper 16: to be downloaded from Campusnet)
Presentations 1 November 2002:
Presentation 11:
8 30 - 9 30
Sequential Test Generation
Presentation by: Martin Hans
Critique by: Alonna Albertus
Literature:
S. Sheng, M.S. Hsiao Efficient Sequential Test Generation Based on
Logic Simulation
IEEE D&T of Computers, Vol. 19/5, pp 56-64, September 2002
(Paper 14: to be downloaded from Campusnet)
Presentations 25 October 2002:
Presentation 10:
8 30 - 9 30
X Algorithm
Presentation by: Christian Park Kjeldsen
Critique by: Felipe Rivera Marquez
Literature:
S.B. Akers, B. Krishnamurthy, S. Park and A. Swaminathan Why is Less Information from Logic Simulation more Useful
in Fault Simulation ? in Proceedings IEEE International Test Conference,
Washington DC, 1990, pp 786 - 800
(Paper 13: to be downloaded from Campusnet)
Presentations 11 October 2002:
Presentation 9:
9 45 - 10 45
Critical Path Tracing - An Alternative to Fault Simulation
Presentation by: Jacob Gregers Hansen
Critique by: Nicolai Ascanius Jørgensen
Literature:
M. Abramovici, P.R. Menon, and D.T. Miller Critical Path Tracing - An Alternative to Fault Simulation
IEEE D&T of Computers, Vol. 1/1, pp 83-93, February 1984
(Paper 12: to be downloaded from Campusnet)
W. Maly and M. Patyra Design of ICs Applying Built-In Current Testing
JETTA-3/4, December 1992, pp 397-406
(Paper 11: to be downloaded from Campusnet)
Presentation 8:
9 45 - 10 45
* CANCELLED *
Critical Path Tracing - An Alternative to Fault Simulation
Presentation by: Christoffer Felix Pedersen
Critique by: Nicolai Ascanius Jørgensen
Literature:
M. Abramovici, P.R. Menon, and D.T. Miller Critical Path Tracing - An Alternative to Fault Simulation
IEEE D&T of Computers, Vol. 1/1, pp 83-93, February 1984
(Paper 12: to be downloaded from Campusnet)
Presentations 27 September 2002:
Presentation 5:
8 30 - 9 30
Bridging fault modeling and Simulation for Deep Submicron CMOS ICs
Presentation by: Felipe Rivera Marquez
Critique by: Christian Park Kjeldsen
Literature:
M. Favalli and M. Dalpasso Bridging Fault Modeling and Simulation for
Deep Submicron CMOS ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems
August 2002, T-CAD-21/8, pp 941-953
(Paper 9: to be downloaded from Campusnet)
Presentation 6:
9 45 - 10 45
Fault Simulation with Parallel Value List Algorithm
Presentation by: Ryan Mitchell Raasch
Critique by: Asger Stenberg Pedersen
Literature:
K. Son Fault Simulation with Parallel Value List Algorithm
VLSI Systems Design, December 1985, 6/12, pp 36-43
(Paper 10: to be downloaded from Campusnet)
Presentations 20 September 2002:
Presentation 3:
8 30 - 9 30
Built-In Current Testing (1)
Presentation by: Michael Kristensen
Critique by: Jon Kaare Christiansen
Literature:
S. Hwang and R. Rajsuman VLSI Testing for High Reliability:
Mixing IDDQ and Logic Testing in Proceedings IEEE ICVC93, November 1993, pp 372-376
(Paper 6: to be downloaded from Campusnet)
Presentation 4:
9 45 - 10 45
Test Generation Using Iterative Array Models
Presentation by: Andreas Vad Lorentzen
Critique by: Xin Meng
Literature:
M. Abramovici, M.A. Breuer, and A.D. Friedman Digital Systems Testing and Testable Design
W.H. Freeman, Computer Science Press, 1990,
Section 6.3.1, pp 249 - 262
(Paper 7: to be downloaded from Campusnet)
Presentations 13 September 2002:
Presentation 1:
8 30 - 9 30
Delay Test Generation 1 - Concepts and Coverage Metrics
Presentation by: Alonna Albertus
Critique by: Martin Hans
Literature:
V.S. Iyengar, B.K. Rosen, I. Spillinger Delay Test Generation 1 - Concepts and Coverage Metrics
1988 IEEE International Test Conference
September 1988, Paper 40.2, pp 857-866
(Paper 3: to be downloaded from Campusnet)
Presentation 2:
9 45 - 10 45
Delay Test Generation 2 - Algebra and Algorithms
Presentation by: Kehuai Wu
Critique by: Jacob Gregers Hansen
Literature:
V.S. Iyengar, B.K. Rosen, I. Spillinger Delay Test Generation 2 - Algebra and Algorithms
1988 IEEE International Test Conference
September 1988, Paper 40.3, pp 867-876
(Paper 4: to be downloaded from Campusnet)
Associate professor Flemming Stassen,
stassen@imm.dtu.dk
