DTU 02208

Course Description

02208 Test of Integrated Circuits
Plan for Lectures 14 through 17:
Built-in self test



Design for test becomes the issue, whenever test pattern generation is considered too complex or costly. The design for test problem can be formulated in terms of the questions
  • How can the testability of a circuit be quantified ?
  • How do we design testable circuits ?
  • How may we take advantage of regular structures ?
  • Can the circuit be designed to test itself ?
The lectures on built-in self test address the techniques used to construct a system capable of testing itself.



Lecture 14: Built-in self-test : Introduction

Purpose:
To discuss the fundamental concepts of Built-In Self-Test
Contents:
Built-In Test and Self-Test
On-chip Test pattern generation
Weighted random patterns
Pseudo-exhaustive patterns
Deterministic patterns
Literature:
241-285

Lectures 15 and 16: Built-in self-test : Signature analysis

Purpose:
To present methods for test data compression
Contents:
On-chip Test response evaluation
Continuous monitoring
Periodic response analysis
Signature analysis
LFSRs and MISRs: a description
The feedback polynomial
Literature:
241-285

Lecture 17: Built-in self-test : BIST planning

Purpose:
To discuss test resource allocation
Contents:
BIST hardware structures
Multifunctional test registers
BILBO register and FRODO cells
Test register allocation and clustering
Test units
Test scheduling
Literature:
O.F. Haberl and H.-J. Wunderlich
The Synthesis of Self-Test Control Logic
in Proceedings CompEuro '89
('VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks')
May 1989, pp 5.134-5.136
(Paper 15: to be downloaded from Campusnet)

Associate professor Flemming Stassen, stassen@imm.dtu.dk