DTU 02208

Course Description

02208 Test of Integrated Circuits
Plan for Lectures 11 through 13:
Design for test



Design for test becomes the issue, whenever test pattern generation is considered too complex or costly. The design for test problem can be formulated in terms of the questions
  • How can the testability of a circuit be quantified ?
  • How do we design testable circuits ?
  • How may we take advantage of regular structures ?
  • Can the circuit be designed to test itself ?
The lectures on design for test address the solutions at systems level.



Lecture 11: Design for test : Ad-hoc techniques

Purpose:
To discuss the fundamental concepts of Design For Test
Contents:
DFT overhead: trading NRE and RE costs
Generic concepts: Controllability and Observability
Ad-hoc DFT techniques: Test points, Partitioning, etc.
A simple example... (see Problem 5.3)
Literature:
Sections 5.1-5.2, pp 201-206

Lecture 12: Design for test : Scan-based design

Purpose:
To present structured approaches to DFT
Contents:
Scan path techniques: Scan design
Single or multiple scan paths
LSSD: Level-Sensitive Scan Design
LSSD design rules
LSSD circuit configurations
LSSD design examples
Literature:
Section 5.3, pp 206-229

Lecture 13: Design for test : Boundary scan

Purpose:
To present methods for addressing the board level test problem
Contents:
In-Circuit testing of PC Boards
Boundary Scan architecture and test modes
TAP : the Test Access Port
Literature:
Section 5.4, pp 230-240
External Resources:
For the playful, Asset InterTech, Inc. provided an online boundary scan tutorial (see the Campusnet)

Associate professor Flemming Stassen, stassen@imm.dtu.dk