Low Power Electronics and Design
Simulation and Synthesis
Circuit Level
Epic's PowerMill
Epic's Vertue
Anagram's ADM
Mentor Graphics' Lsim Power Analyst
Epic's AMPS
Gate Level
Synopsys' DesignPower
PowerSIM
from Electronic Engineering Times Design Automation Special -- News
Veritool's Power tool
Sente, Inc. Watt Watcher
Viewlogic's POET
The Xpower Dynamic Power Analysis and Display Program
Synopsys' PowerCompiler
Higher Level
Top-Down Design Planner - TDP Product Overview
ASC's VHDL Behavioral Synthesis for Low Power
Simulators
Synopsys' VSS - Simulation
Cadence's Verilog-XL
Mentor Graphics' V-XL Co-Lsim
Viewlogic Simulation Tools
The Simic Logic Simulator
FrontLine Product Information
University's Tools
USC's Power Optimization and Synthesis Environment
Stanford's PPP
PET - Power Evaluation Tool
Alberto Nannarelli
( alberto@ece.uci.edu )