Interconnect-Centic Design for Advanced SoC and NoC

Credits: 5 ECTS

Description

In this course and its textbook, we are trying to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design.

The topic of interconnect-centric design was seen very important especially after writing the previous book (Networks on Chip) where the higher-level on-chip communication issues were tackled. The enthusiastic embrace of the SoC vision has cooled down considerably over the last one or two years, as the approach has run into some major roadblocks and hurdles. While these challenges were already speculated on in the mid 90’s, they have come into full bearing today. The combination of deep submicron effects, manufacturing cost, and complexity have caused a major shift in the economics of IC design, and have marked the beginning of the end of the era of the Application Specific Integrated Circuit. Instead, a new design methodology called “platform-based design” has been proposed, promoting reuse at higher levels of granularity and relying heavily on flexibility and programmability to amortize the NRE costs of complex IC design over a number of designs. With SoC integration, implementation platforms are becoming more diverse and heterogeneous, combining various implementation strategies with diverging flexibility, granularity, performance, and energy-efficiency properties.

The on-chip communication is in increasingly important role in deep submicron technologies. The decreasing spacing of wires together with increasing transition frequencies bring along capacitive and inductive crosstalk, transmission line effects, propagation delay and power distribution problems. The most viable approach to cope with the interconnects is to use a layered approach familiar from macro-world communication networks. This approach can be generally called Network-on-Chip.

This course concentrates on the interconnects, on-chip communication on different abstraction levels and on interconnect-centric design as a solution to the challenges imposed by the deep submicron technologies. We will take a look at design methodologies for wires acting as inductive interconnects in highly integrated systems. Global interconnect analysis and interconnect modelling as methodology are overviewed. Signaling approaches taking into account power, performance and noise immunity will be discussed. Clock generation and distribution strategies in complex high-performance circuits will be disclosed. The next step is to look at interconnects as buses, including the characteristics and limitations of shared interconnects. One solution to flexible and dependable high-bandwidth communication is to use on-chip network constructs instead of buses. Self-timed approach is forming the cornerstone of GALS (Globally Asynchronous Locally Synchronous) design methodology. In addition to that, self-timed design can be used for noise reduction purposes at the same time. Formal refinement methodology for the on-chip communication is also presented on the course. High-level modeling of communicating processes in multiprocessor systems is a higher abstraction level solution to interconnect-aware design. Finally, a practical design approach using decoupled interconnects will be introduced, and two different application cases conclude the course.