To provide the participants with in depth knowledge on computer organization, and an associated understanding of issues which influence the run-time of programs as well as an understanding of the interplay between hardware end software.

Today processors are used in all forms of electronic equipment and hence the course is relevant for software developers as well as (electrical) engineers designing embedded systems where it is often important to make efficient use of the resources of the processor in order to optimize performance, cost or energy consumption

• Describe the internal structure of a processor, including pipeline, cache mamory, memory hierarchy, virtual memory, busses, etc.
• Explain the function of these elements and explain how they influence the runtime of programs, and the complexity of the underlying hardware (area, speed and energy).
• Apply this knowledge to calculate and optimize the run-time of programs; both small program fragments and large programs for which key parameters like cache-miss rates have been established.
• Explain the parameters throughput and latency, and explain the relationship between these parameters.
• Explain how hardware (e.g. technology and architecture) and software (i.g. instruction set, compiler and operating system) forms a whole, and that the interface between the two is a key element in all systems
• Give examples of trade-off and optimizations involving both hardware and software
• Explain the instruction set architecture of a typical processor.
• Document project work in the form of a technical report addressing engineers in the field. The report must conform to usual requirements to form, content and level of abstraction.

Computer organization: Introduction to computer organization and instruction sets. Organization of the processor in a modern RISC-computer (control unit, data path, pipelining). The relationship between processor organization and instruction set. Buses and I/O units and between processor organization and operating systems. Memory hierarchies, cache memories and virtual memory. New architectures which exploit different forms of parallelism.

In parallel with the lectures students work on problems and exercises and towards the end of the course students work on a final small project. The project can for example be to analyze and optimize the runtime of a given program by considering the processors pipeline structure and memory hierarchy using a simulator.